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authorIgor Mammedov <imammedo@redhat.com>2020-02-19 11:09:24 -0500
committerPatchew Importer <importer@patchew.org>2020-02-19 16:49:59 +0000
commit9389d6ce0b893542524611f319b57df3e181957a (patch)
treee3e1927076dce22f5a56c605c1b3008f5cbac48a /hw/mips
parent49b64ba90649b28851bf7fc6377810a411d55386 (diff)
mips/boston: use memdev for RAM
memory_region_allocate_system_memory() API is going away, so replace it with memdev allocated MemoryRegion. The later is initialized by generic code, so board only needs to opt in to memdev scheme by providing MachineClass::default_ram_id and using MachineState::ram instead of manually initializing RAM memory region. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20200219160953.13771-51-imammedo@redhat.com>
Diffstat (limited to 'hw/mips')
-rw-r--r--hw/mips/boston.c11
1 files changed, 5 insertions, 6 deletions
diff --git a/hw/mips/boston.c b/hw/mips/boston.c
index 0df3a7755a..98ecd25e8e 100644
--- a/hw/mips/boston.c
+++ b/hw/mips/boston.c
@@ -427,7 +427,7 @@ static void boston_mach_init(MachineState *machine)
DeviceState *dev;
BostonState *s;
Error *err = NULL;
- MemoryRegion *flash, *ddr, *ddr_low_alias, *lcd, *platreg;
+ MemoryRegion *flash, *ddr_low_alias, *lcd, *platreg;
MemoryRegion *sys_mem = get_system_memory();
XilinxPCIEHost *pcie2;
PCIDevice *ahci;
@@ -473,14 +473,12 @@ static void boston_mach_init(MachineState *machine)
memory_region_init_rom(flash, NULL, "boston.flash", 128 * MiB, &err);
memory_region_add_subregion_overlap(sys_mem, 0x18000000, flash, 0);
- ddr = g_new(MemoryRegion, 1);
- memory_region_allocate_system_memory(ddr, NULL, "boston.ddr",
- machine->ram_size);
- memory_region_add_subregion_overlap(sys_mem, 0x80000000, ddr, 0);
+ memory_region_add_subregion_overlap(sys_mem, 0x80000000, machine->ram, 0);
ddr_low_alias = g_new(MemoryRegion, 1);
memory_region_init_alias(ddr_low_alias, NULL, "boston_low.ddr",
- ddr, 0, MIN(machine->ram_size, (256 * MiB)));
+ machine->ram, 0,
+ MIN(machine->ram_size, (256 * MiB)));
memory_region_add_subregion_overlap(sys_mem, 0, ddr_low_alias, 0);
xilinx_pcie_init(sys_mem, 0,
@@ -552,6 +550,7 @@ static void boston_mach_class_init(MachineClass *mc)
mc->init = boston_mach_init;
mc->block_default_type = IF_IDE;
mc->default_ram_size = 1 * GiB;
+ mc->default_ram_id = "boston.ddr";
mc->max_cpus = 16;
mc->default_cpu_type = MIPS_CPU_TYPE_NAME("I6400");
}