diff options
author | Matthew Fortune <matthew.fortune@imgtec.com> | 2015-06-19 11:08:41 +0100 |
---|---|---|
committer | Leon Alrae <leon.alrae@imgtec.com> | 2015-06-26 09:08:50 +0100 |
commit | d6ca4277eee98b3c561e21ac105199891d346d79 (patch) | |
tree | 750c11cfde2b13a98e5bb45eebe9068c2eaa09ee /hw/mips | |
parent | 9f6f7ca1490563d98003149e6de32caf25c670da (diff) |
hw/mips: Do not clear BEV for MIPS malta kernel load
The BEV flag controls whether the boot exception vector is still
in place when starting a kernel. When cleared the exception vector
at EBASE (or hard coded address of 0x80000000) is used instead.
The early stages of the linux kernel would benefit from BEV still
being set to ensure any faults get handled by the boot rom exception
handlers. This is a moot point for system qemu as there aren't really
any BEV handlers, but there are other good reasons to change this...
The UHI (semi-hosting interface) defines special behaviours depending
on whether an application starts in an environment with BEV set or
cleared. When BEV is set then UHI assumes that a bootloader is
relatively dumb and has no advanced exception handling logic.
However, when BEV is cleared then UHI assumes that the bootloader
has the ability to handle UHI exceptions with its exception handlers
and will unwind and forward UHI SYSCALL exceptions to the exception
vector that was installed prior to running the application.
Signed-off-by: Matthew Fortune <matthew.fortune@imgtec.com>
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Diffstat (limited to 'hw/mips')
-rw-r--r-- | hw/mips/mips_malta.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c index 786a8f0638..a5d64d5030 100644 --- a/hw/mips/mips_malta.c +++ b/hw/mips/mips_malta.c @@ -887,7 +887,7 @@ static void main_cpu_reset(void *opaque) read only location. The kernel location and the arguments table location does not change. */ if (loaderparams.kernel_filename) { - env->CP0_Status &= ~((1 << CP0St_BEV) | (1 << CP0St_ERL)); + env->CP0_Status &= ~(1 << CP0St_ERL); } malta_mips_config(cpu); |