diff options
| author | Peter Maydell <peter.maydell@linaro.org> | 2020-06-01 13:43:59 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2020-06-01 13:43:59 +0100 |
| commit | 7ea32024c6b3ad9c88d6200e73dbf76c8e160024 (patch) | |
| tree | 12a5614f941dc569bad49b858376b6a60b24607e /hw/mips | |
| parent | b73f417aaeeedee933aa031d6430ecb9ada71ccb (diff) | |
| parent | a08d60bc6c2b6469368fff3d38dd5ddd16dd36be (diff) | |
Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-june-01-2020' into staging
MIPS queue for June 1st, 2020
# gpg: Signature made Mon 01 Jun 2020 12:29:25 BST
# gpg: using RSA key D4972A8967F75A65
# gpg: Good signature from "Aleksandar Markovic <amarkovic@wavecomp.com>" [full]
# Primary key fingerprint: 8526 FBF1 5DA3 811F 4A01 DD75 D497 2A89 67F7 5A65
* remotes/amarkovic/tags/mips-queue-june-01-2020:
hw/mips: fuloong2e: Set preferred page size to 16KB
target/mips: Support variable page size
target/mips: Add more CP0 register for save/restore
hw/mips: Add CPU IRQ3 delivery for KVM
configure: Add KVM target support for MIPS64
tests/Makefile: Fix description of "make check"
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/mips')
| -rw-r--r-- | hw/mips/fuloong2e.c | 1 | ||||
| -rw-r--r-- | hw/mips/mips_int.c | 2 |
2 files changed, 2 insertions, 1 deletions
diff --git a/hw/mips/fuloong2e.c b/hw/mips/fuloong2e.c index f583c44b79..7a65166cf0 100644 --- a/hw/mips/fuloong2e.c +++ b/hw/mips/fuloong2e.c @@ -392,6 +392,7 @@ static void mips_fuloong2e_machine_init(MachineClass *mc) mc->default_cpu_type = MIPS_CPU_TYPE_NAME("Loongson-2E"); mc->default_ram_size = 256 * MiB; mc->default_ram_id = "fuloong2e.ram"; + mc->minimum_page_bits = 14; } DEFINE_MACHINE("fuloong2e", mips_fuloong2e_machine_init) diff --git a/hw/mips/mips_int.c b/hw/mips/mips_int.c index 4a1bf846da..0f9c6f07c1 100644 --- a/hw/mips/mips_int.c +++ b/hw/mips/mips_int.c @@ -51,7 +51,7 @@ static void cpu_mips_irq_request(void *opaque, int irq, int level) env->CP0_Cause &= ~(1 << (irq + CP0Ca_IP)); } - if (kvm_enabled() && irq == 2) { + if (kvm_enabled() && (irq == 2 || irq == 3)) { kvm_mips_set_interrupt(cpu, irq, level); } |