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authorPaolo Bonzini <pbonzini@redhat.com>2013-06-06 05:41:28 -0400
committerPaolo Bonzini <pbonzini@redhat.com>2013-07-04 17:42:44 +0200
commit2c9b15cab12c21e32dffb67c5e18f3dc407ca224 (patch)
tree7820aa814c6ee986999c522f3b98ef4e78f91240 /hw/mips/mips_malta.c
parent5767e4e19835cd39de9945bba17438e368e253bb (diff)
memory: add owner argument to initialization functions
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'hw/mips/mips_malta.c')
-rw-r--r--hw/mips/mips_malta.c10
1 files changed, 5 insertions, 5 deletions
diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
index 8a4459d0b2..c27ed0b8ed 100644
--- a/hw/mips/mips_malta.c
+++ b/hw/mips/mips_malta.c
@@ -446,11 +446,11 @@ static MaltaFPGAState *malta_fpga_init(MemoryRegion *address_space,
s = (MaltaFPGAState *)g_malloc0(sizeof(MaltaFPGAState));
- memory_region_init_io(&s->iomem, &malta_fpga_ops, s,
+ memory_region_init_io(&s->iomem, NULL, &malta_fpga_ops, s,
"malta-fpga", 0x100000);
- memory_region_init_alias(&s->iomem_lo, "malta-fpga",
+ memory_region_init_alias(&s->iomem_lo, NULL, "malta-fpga",
&s->iomem, 0, 0x900);
- memory_region_init_alias(&s->iomem_hi, "malta-fpga",
+ memory_region_init_alias(&s->iomem_hi, NULL, "malta-fpga",
&s->iomem, 0xa00, 0x10000-0xa00);
memory_region_add_subregion(address_space, base, &s->iomem_lo);
@@ -853,7 +853,7 @@ void mips_malta_init(QEMUMachineInitArgs *args)
((unsigned int)ram_size / (1 << 20)));
exit(1);
}
- memory_region_init_ram(ram, "mips_malta.ram", ram_size);
+ memory_region_init_ram(ram, NULL, "mips_malta.ram", ram_size);
vmstate_register_ram_global(ram);
memory_region_add_subregion(system_memory, 0, ram);
@@ -927,7 +927,7 @@ void mips_malta_init(QEMUMachineInitArgs *args)
}
/* Map the BIOS at a 2nd physical location, as on the real board. */
- memory_region_init_alias(bios_alias, "bios.1fc", bios, 0, BIOS_SIZE);
+ memory_region_init_alias(bios_alias, NULL, "bios.1fc", bios, 0, BIOS_SIZE);
memory_region_add_subregion(system_memory, RESET_ADDRESS, bios_alias);
/* Board ID = 0x420 (Malta Board with CoreLV)