diff options
| author | Leon Alrae <leon.alrae@imgtec.com> | 2016-03-28 19:35:52 -0700 |
|---|---|---|
| committer | Leon Alrae <leon.alrae@imgtec.com> | 2016-07-12 09:10:13 +0100 |
| commit | 19494f811a43c6bc226aa272d86300d9229224fe (patch) | |
| tree | 50d232e81783cb853b087fad2a3cd98495309818 /hw/mips/mips_malta.c | |
| parent | e8bd336dd1af6d1073e9411bd1c47b045988b30a (diff) | |
hw/mips/cps: create GIC block inside CPS
Add GIC to CPS and expose its interrupt pins instead of CPU's.
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Diffstat (limited to 'hw/mips/mips_malta.c')
| -rw-r--r-- | hw/mips/mips_malta.c | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c index 5c8ba44c62..34d41ef44a 100644 --- a/hw/mips/mips_malta.c +++ b/hw/mips/mips_malta.c @@ -955,9 +955,7 @@ static void create_cps(MaltaState *s, const char *cpu_model, sysbus_mmio_map_overlap(SYS_BUS_DEVICE(s->cps), 0, 0, 1); - /* FIXME: When GIC is present then we should use GIC's IRQ 3. - Until then CPS exposes CPU's IRQs thus use the default IRQ 2. */ - *i8259_irq = get_cps_irq(s->cps, 2); + *i8259_irq = get_cps_irq(s->cps, 3); *cbus_irq = NULL; } |