diff options
| author | Huacai Chen <zltjiangshi@gmail.com> | 2020-05-03 18:20:17 +0800 |
|---|---|---|
| committer | Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> | 2020-06-01 13:28:21 +0200 |
| commit | c3173a35bc2a759dbfac4e76e9a7695b1d44e97a (patch) | |
| tree | ed928f9c75b04bfa9a4d8f5dffaca754a323d79b /hw/mips/mips_int.c | |
| parent | aa2953fd169c98c6ef44feb9c7e44eaad7f2808b (diff) | |
hw/mips: Add CPU IRQ3 delivery for KVM
Currently, KVM/MIPS only deliver I/O interrupt via IP2, this patch add
IP3 delivery as well, because Loongson-3 based machine use both IRQ2
(CPU's IP2) and IRQ3 (CPU's IP3).
Signed-off-by: Huacai Chen <chenhc@lemote.com>
Co-developed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
Message-Id: <1588501221-1205-4-git-send-email-chenhc@lemote.com>
Diffstat (limited to 'hw/mips/mips_int.c')
| -rw-r--r-- | hw/mips/mips_int.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/hw/mips/mips_int.c b/hw/mips/mips_int.c index 4a1bf846da..0f9c6f07c1 100644 --- a/hw/mips/mips_int.c +++ b/hw/mips/mips_int.c @@ -51,7 +51,7 @@ static void cpu_mips_irq_request(void *opaque, int irq, int level) env->CP0_Cause &= ~(1 << (irq + CP0Ca_IP)); } - if (kvm_enabled() && irq == 2) { + if (kvm_enabled() && (irq == 2 || irq == 3)) { kvm_mips_set_interrupt(cpu, irq, level); } |