diff options
| author | Philippe Mathieu-Daudé <philmd@linaro.org> | 2022-10-26 01:54:46 +0200 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <philmd@linaro.org> | 2023-01-13 09:32:32 +0100 |
| commit | 1953dfa80e0fc44a8ccfc97b4ada941e9383bba7 (patch) | |
| tree | 4a10dfb77a62495b497370efc9a7e3bba6d8c5c1 /hw/mips/malta.c | |
| parent | 6dd92ce6c541d331f384b808173b7c97c09c8684 (diff) | |
hw/mips/malta: Set PIIX4 IRQ routes in embedded bootloader
Linux kernel expects the northbridge & southbridge chipsets
configured by the BIOS firmware. We emulate that by writing
a tiny bootloader code in write_bootloader().
Upon introduction in commit 5c2b87e34d ("PIIX4 support"),
the PIIX4 configuration space included values specific to
the Malta board.
Set the Malta-specific IRQ routing values in the embedded
bootloader, so the next commit can remove the Malta specific
bits from the PIIX4 PCI-ISA bridge and make it generic
(matching the real hardware).
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20221027204720.33611-3-philmd@linaro.org>
Diffstat (limited to 'hw/mips/malta.c')
| -rw-r--r-- | hw/mips/malta.c | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/hw/mips/malta.c b/hw/mips/malta.c index 9fc3280407..ae76b4db70 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -621,6 +621,10 @@ static void network_init(PCIBus *pci_bus) static void bl_setup_gt64120_jump_kernel(void **p, uint64_t run_addr, uint64_t kernel_entry) { + static const char pci_pins_cfg[PCI_NUM_PINS] = { + 10, 10, 11, 11 /* PIIX IRQRC[A:D] */ + }; + /* Bus endianess is always reversed */ #if TARGET_BIG_ENDIAN #define cpu_to_gt32 cpu_to_le32 @@ -659,6 +663,20 @@ static void bl_setup_gt64120_jump_kernel(void **p, uint64_t run_addr, #undef cpu_to_gt32 + /* + * The PIIX ISA bridge is on PCI bus 0 dev 10 func 0. + * Load the PIIX IRQC[A:D] routing config address, then + * write routing configuration to the config data register. + */ + bl_gen_write_u32(p, /* GT_PCI0_CFGADDR */ + cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0xcf8), + tswap32((1 << 31) /* ConfigEn */ + | PCI_BUILD_BDF(0, PIIX4_PCI_DEVFN) << 8 + | PIIX_PIRQCA)); + bl_gen_write_u32(p, /* GT_PCI0_CFGDATA */ + cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0xcfc), + tswap32(ldl_be_p(pci_pins_cfg))); + bl_gen_jump_kernel(p, true, ENVP_VADDR - 64, /* |