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authorPeter Maydell <peter.maydell@linaro.org>2022-04-08 15:15:11 +0100
committerPeter Maydell <peter.maydell@linaro.org>2022-04-22 09:19:24 +0100
commit89ac9d0cba3c5d86c4a19ba1cd139ad25d041826 (patch)
tree41aee15c6b034c649f7c9e8ebbdbad769f575674 /hw/intc
parent2a1990369719e3e202188236483bab0208a87d24 (diff)
hw/intc/arm_gicv3: Sanity-check num-cpu property
In the GICv3 code we implicitly rely on there being at least one CPU and thus at least one redistributor and CPU interface. Sanity-check that the property the board code sets is not zero. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220408141550.1271295-3-peter.maydell@linaro.org
Diffstat (limited to 'hw/intc')
-rw-r--r--hw/intc/arm_gicv3_common.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c
index 4ca5ae9bc5..90204be25b 100644
--- a/hw/intc/arm_gicv3_common.c
+++ b/hw/intc/arm_gicv3_common.c
@@ -328,6 +328,10 @@ static void arm_gicv3_common_realize(DeviceState *dev, Error **errp)
s->num_irq, GIC_INTERNAL);
return;
}
+ if (s->num_cpu == 0) {
+ error_setg(errp, "num-cpu must be at least 1");
+ return;
+ }
/* ITLinesNumber is represented as (N / 32) - 1, so this is an
* implementation imposed restriction, not an architectural one,