diff options
| author | Cédric Le Goater <clg@kaod.org> | 2019-11-25 07:58:07 +0100 |
|---|---|---|
| committer | David Gibson <david@gibson.dropbear.id.au> | 2019-12-17 10:39:48 +1100 |
| commit | 119eaa9d11cb5245fae0a2cbe4f18dda55744dfb (patch) | |
| tree | aa8e92c412f620692503485aea610be4e25f2a57 /hw/intc | |
| parent | 5014c60261cf38b7c210831548c042982218a999 (diff) | |
ppc/pnv: Fix TIMA indirect access
When the TIMA of a CPU needs to be accessed from the indirect page,
the thread id of the target CPU is first stored in the PC_TCTXT_INDIR0
register. This thread id is relative to the chip and not to the system.
Introduce a helper routine to look for a CPU of a given PIR and fix
pnv_xive_get_indirect_tctx() to scan only the threads of the local
chip and not the whole machine.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20191125065820.927-8-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'hw/intc')
| -rw-r--r-- | hw/intc/pnv_xive.c | 13 |
1 files changed, 7 insertions, 6 deletions
diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c index ec8349ee4a..b2ab2ccc91 100644 --- a/hw/intc/pnv_xive.c +++ b/hw/intc/pnv_xive.c @@ -1400,12 +1400,13 @@ static const MemoryRegionOps pnv_xive_ic_lsi_ops = { */ /* - * When the TIMA is accessed from the indirect page, the thread id - * (PIR) has to be configured in the IC registers before. This is used - * for resets and for debug purpose also. + * When the TIMA is accessed from the indirect page, the thread id of + * the target CPU is configured in the PC_TCTXT_INDIR0 register before + * use. This is used for resets and for debug purpose also. */ static XiveTCTX *pnv_xive_get_indirect_tctx(PnvXive *xive) { + PnvChip *chip = xive->chip; uint64_t tctxt_indir = xive->regs[PC_TCTXT_INDIR0 >> 3]; PowerPCCPU *cpu = NULL; int pir; @@ -1415,15 +1416,15 @@ static XiveTCTX *pnv_xive_get_indirect_tctx(PnvXive *xive) return NULL; } - pir = GETFIELD(PC_TCTXT_INDIR_THRDID, tctxt_indir) & 0xff; - cpu = ppc_get_vcpu_by_pir(pir); + pir = (chip->chip_id << 8) | GETFIELD(PC_TCTXT_INDIR_THRDID, tctxt_indir); + cpu = pnv_chip_find_cpu(chip, pir); if (!cpu) { xive_error(xive, "IC: invalid PIR %x for indirect access", pir); return NULL; } /* Check that HW thread is XIVE enabled */ - if (!(xive->regs[PC_THREAD_EN_REG0 >> 3] & PPC_BIT(pir & 0x3f))) { + if (!pnv_xive_is_cpu_enabled(xive, cpu)) { xive_error(xive, "IC: CPU %x is not enabled", pir); } |