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authorAlistair Francis <alistair.francis@wdc.com>2021-08-30 15:34:20 +1000
committerAlistair Francis <alistair.francis@wdc.com>2021-09-21 07:56:49 +1000
commit0f0b70eeecdd4e0f29efe28a7ffec01cbe5c43bf (patch)
treed375b12954a4b939bc8a135790b7450b7a56d9eb /hw/intc
parent15732b8ed290460334ee58dd25939da733f362fd (diff)
target/riscv: Expose interrupt pending bits as GPIO lines
Expose the 12 interrupt pending bits in MIP as GPIO lines. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 069d6162f0bc2f4a4f5a44e73f6442b11c703c53.1630301632.git.alistair.francis@wdc.com
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