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authorAndrew Jeffery <andrew@aj.id.au>2018-07-16 17:18:41 +0100
committerPeter Maydell <peter.maydell@linaro.org>2018-07-16 17:18:41 +0100
commit333b9c8a684c58f6711521e446e4b26de5addadc (patch)
tree58025693c3940e354eb86b3402c476422740f335 /hw/intc
parent628fc75f3a3bb115de3b445c1a18547c44613cfe (diff)
aspeed: Implement write-1-{set, clear} for AST2500 strapping
The AST2500 SoC family changes the runtime behaviour of the hardware strapping register (SCU70) to write-1-set/write-1-clear, with write-1-clear implemented on the "read-only" SoC revision register (SCU7C). For the the AST2400, the hardware strapping is runtime-configured with read-modify-write semantics. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Message-id: 20180709143524.17480-1-andrew@aj.id.au Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/intc')
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