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authorJim Shu <jim.shu@sifive.com>2022-10-03 04:14:39 +0000
committerAlistair Francis <alistair.francis@wdc.com>2022-10-14 14:29:50 +1000
commit55144a1fd0d1f37b49ea051291decbbe427b7714 (patch)
tree9843c9302248ba7960a9191c3b43a6a2c9912575 /hw/intc/xive.c
parent07f4964d1785e9c230282074a5aef1eb7368d378 (diff)
hw/intc: sifive_plic: fix hard-coded max priority level
The maximum priority level is hard-coded when writing to interrupt priority register. However, when writing to priority threshold register, the maximum priority level is from num_priorities Property which is configured by platform. Also change interrupt priority register to use num_priorities Property in maximum priority level. Signed-off-by: Emmanuel Blot <emmanuel.blot@sifive.com> Signed-off-by: Jim Shu <jim.shu@sifive.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20221003041440.2320-2-jim.shu@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/intc/xive.c')
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