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authorPeter Maydell <peter.maydell@linaro.org>2017-04-26 13:17:11 +0100
committerPeter Maydell <peter.maydell@linaro.org>2017-04-26 13:17:11 +0100
commitdcaed66cbe2803f9378f3a043c2e482bf8035dfd (patch)
treea5611646eb333ac5b2e7049e3e165df8d742530f /hw/intc/xics_spapr.c
parent52e94ea5de3ed9d7ddf1b0e5fc6ff7c2807ae711 (diff)
parentdf02d2ca8b23ba1fff137090a65731c68cf1393d (diff)
Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-2.10-20170426' into staging
ppc patch queue 2017-04-26 Here's a respind of my first pull request for qemu-2.10, consisting of assorted patches which have accumulated while qemu-2.9 stabilized. Highlights are: * Rework / cleanup of the XICS interrupt controller * Substantial improvement to the 'powernv' machine type - Includes an MMIO XICS version * POWER9 support improvements - POWER9 guests with KVM - Partial support for POWER9 guests with TCG * IOMMU and VFIO improvements * Assorted minor changes There are several IPMI patches here that aren't usually in my area of maintenance, but there isn't a regular maintainer and these patches are for the benefit of the powernv machine type. This pull request supersedes my 2017-04-26 pull request. This new set fixes a bug in one of the aforementioned IPMI patches which caused clang sanitizer failures (and may have crashed on some libc / host versions). # gpg: Signature made Wed 26 Apr 2017 07:58:10 BST # gpg: using RSA key 0x6C38CACA20D9B392 # gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" # gpg: aka "David Gibson (Red Hat) <dgibson@redhat.com>" # gpg: aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>" # gpg: aka "David Gibson (kernel.org) <dwg@kernel.org>" # Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392 * remotes/dgibson/tags/ppc-for-2.10-20170426: (48 commits) MAINTAINERS: Remove myself from e500 target/ppc: Style fixes e500,book3s: mfspr 259: Register mapped/aliased SPRG3 user read target/ppc: Flush TLB on write to PIDR spapr-cpu-core: Release ICPState object during CPU unrealization ppc/pnv: generate an OEM SEL event on shutdown ppc/pnv: add initial IPMI sensors for the BMC simulator ppc/pnv: populate device tree for IPMI BT devices ppc/pnv: populate device tree for serial devices ppc/pnv: populate device tree for RTC devices ppc/pnv: scan ISA bus to populate device tree ppc/pnv: enable only one LPC bus ppc/pnv: Add support for POWER8+ LPC Controller spapr: remove the 'nr_servers' field from the machine target/ppc: Fix size of struct PPCElfPrstatus ipmi: introduce an ipmi_bmc_gen_event() API ipmi: introduce an ipmi_bmc_sdr_find() API ipmi: provide support for FRUs ipmi: use a file to load SDRs ppc: add IPMI support ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/intc/xics_spapr.c')
-rw-r--r--hw/intc/xics_spapr.c25
1 files changed, 7 insertions, 18 deletions
diff --git a/hw/intc/xics_spapr.c b/hw/intc/xics_spapr.c
index 84d24b2837..f05308b897 100644
--- a/hw/intc/xics_spapr.c
+++ b/hw/intc/xics_spapr.c
@@ -43,20 +43,17 @@
static target_ulong h_cppr(PowerPCCPU *cpu, sPAPRMachineState *spapr,
target_ulong opcode, target_ulong *args)
{
- CPUState *cs = CPU(cpu);
- ICPState *icp = xics_icp_get(XICS_FABRIC(spapr), cs->cpu_index);
target_ulong cppr = args[0];
- icp_set_cppr(icp, cppr);
+ icp_set_cppr(ICP(cpu->intc), cppr);
return H_SUCCESS;
}
static target_ulong h_ipi(PowerPCCPU *cpu, sPAPRMachineState *spapr,
target_ulong opcode, target_ulong *args)
{
- target_ulong server = xics_get_cpu_index_by_dt_id(args[0]);
target_ulong mfrr = args[1];
- ICPState *icp = xics_icp_get(XICS_FABRIC(spapr), server);
+ ICPState *icp = xics_icp_get(XICS_FABRIC(spapr), args[0]);
if (!icp) {
return H_PARAMETER;
@@ -69,9 +66,7 @@ static target_ulong h_ipi(PowerPCCPU *cpu, sPAPRMachineState *spapr,
static target_ulong h_xirr(PowerPCCPU *cpu, sPAPRMachineState *spapr,
target_ulong opcode, target_ulong *args)
{
- CPUState *cs = CPU(cpu);
- ICPState *icp = xics_icp_get(XICS_FABRIC(spapr), cs->cpu_index);
- uint32_t xirr = icp_accept(icp);
+ uint32_t xirr = icp_accept(ICP(cpu->intc));
args[0] = xirr;
return H_SUCCESS;
@@ -80,9 +75,7 @@ static target_ulong h_xirr(PowerPCCPU *cpu, sPAPRMachineState *spapr,
static target_ulong h_xirr_x(PowerPCCPU *cpu, sPAPRMachineState *spapr,
target_ulong opcode, target_ulong *args)
{
- CPUState *cs = CPU(cpu);
- ICPState *icp = xics_icp_get(XICS_FABRIC(spapr), cs->cpu_index);
- uint32_t xirr = icp_accept(icp);
+ uint32_t xirr = icp_accept(ICP(cpu->intc));
args[0] = xirr;
args[1] = cpu_get_host_ticks();
@@ -92,21 +85,17 @@ static target_ulong h_xirr_x(PowerPCCPU *cpu, sPAPRMachineState *spapr,
static target_ulong h_eoi(PowerPCCPU *cpu, sPAPRMachineState *spapr,
target_ulong opcode, target_ulong *args)
{
- CPUState *cs = CPU(cpu);
- ICPState *icp = xics_icp_get(XICS_FABRIC(spapr), cs->cpu_index);
target_ulong xirr = args[0];
- icp_eoi(icp, xirr);
+ icp_eoi(ICP(cpu->intc), xirr);
return H_SUCCESS;
}
static target_ulong h_ipoll(PowerPCCPU *cpu, sPAPRMachineState *spapr,
target_ulong opcode, target_ulong *args)
{
- CPUState *cs = CPU(cpu);
- ICPState *icp = xics_icp_get(XICS_FABRIC(spapr), cs->cpu_index);
uint32_t mfrr;
- uint32_t xirr = icp_ipoll(icp, &mfrr);
+ uint32_t xirr = icp_ipoll(ICP(cpu->intc), &mfrr);
args[0] = xirr;
args[1] = mfrr;
@@ -132,7 +121,7 @@ static void rtas_set_xive(PowerPCCPU *cpu, sPAPRMachineState *spapr,
}
nr = rtas_ld(args, 0);
- server = xics_get_cpu_index_by_dt_id(rtas_ld(args, 1));
+ server = rtas_ld(args, 1);
priority = rtas_ld(args, 2);
if (!ics_valid_irq(ics, nr) || !xics_icp_get(XICS_FABRIC(spapr), server)