diff options
| author | Cédric Le Goater <clg@kaod.org> | 2022-03-02 06:51:39 +0100 |
|---|---|---|
| committer | Cédric Le Goater <clg@kaod.org> | 2022-03-02 06:51:39 +0100 |
| commit | 835806f1f97a840d27e9c2e24c678af6e12b2dc4 (patch) | |
| tree | 8c49c2d22daa937bfa8a3f7c3ce6da808cdef7fa /hw/intc/pnv_xive2.c | |
| parent | e16032b8dc56332096111ce02741a03c88c7be43 (diff) | |
pnv/xive2: Add support for automatic save&restore
The XIVE interrupt controller on P10 can automatically save and
restore the state of the interrupt registers under the internal NVP
structure representing the VCPU. This saves a costly store/load in
guest entries and exits.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Diffstat (limited to 'hw/intc/pnv_xive2.c')
| -rw-r--r-- | hw/intc/pnv_xive2.c | 18 |
1 files changed, 17 insertions, 1 deletions
diff --git a/hw/intc/pnv_xive2.c b/hw/intc/pnv_xive2.c index 963f6ad2da..b51571c603 100644 --- a/hw/intc/pnv_xive2.c +++ b/hw/intc/pnv_xive2.c @@ -435,6 +435,10 @@ static uint32_t pnv_xive2_get_config(Xive2Router *xrtr) cfg |= XIVE2_GEN1_TIMA_OS; } + if (xive->cq_regs[CQ_XIVE_CFG >> 3] & CQ_XIVE_CFG_EN_VP_SAVE_RESTORE) { + cfg |= XIVE2_VP_SAVE_RESTORE; + } + return cfg; } @@ -2000,9 +2004,21 @@ static void xive2_nvp_pic_print_info(Xive2Nvp *nvp, uint32_t nvp_idx, return; } - monitor_printf(mon, " %08x end:%02x/%04x IPB:%02x\n", + monitor_printf(mon, " %08x end:%02x/%04x IPB:%02x", nvp_idx, eq_blk, eq_idx, xive_get_field32(NVP2_W2_IPB, nvp->w2)); + /* + * When the NVP is HW controlled, more fields are updated + */ + if (xive2_nvp_is_hw(nvp)) { + monitor_printf(mon, " CPPR:%02x", + xive_get_field32(NVP2_W2_CPPR, nvp->w2)); + if (xive2_nvp_is_co(nvp)) { + monitor_printf(mon, " CO:%04x", + xive_get_field32(NVP2_W1_CO_THRID, nvp->w1)); + } + } + monitor_printf(mon, "\n"); } /* |