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authorPeter Maydell <peter.maydell@linaro.org>2014-05-07 17:16:03 +0100
committerPeter Maydell <peter.maydell@linaro.org>2014-05-07 17:16:03 +0100
commitb18a990c3d5cb8f8dfe1a5e5b36c67857ce1cf86 (patch)
treea8a6d9eb85d43bee1905bf99cf04d73ddfb5db37 /hw/intc/i8259.c
parent8d1dc5d188b84a2b2aeb9bd39fddb3d2c67be60c (diff)
parentcab00a5aa163b6bba3043ef0636c4a3a061511ec (diff)
Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging
pc,net,MAINTAINERS,build updates MAINTAINERS updated with link to the security process documentation apic version modified to make more guests happy On top of that, bugfixes all over the place Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # gpg: Signature made Wed 07 May 2014 17:15:29 BST using RSA key ID D28D5469 # gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" # gpg: aka "Michael S. Tsirkin <mst@redhat.com>" * remotes/mst/tags/for_upstream: configure: make source tree build more robust MAINTAINERS: addresses for responsible disclosure pm_smbus: correctly report unclaimed cycles smbus: return -1 if nothing found at the given address smbus: allow returning an error from reads apic: use emulated lapic version 0x14 on pc machines >= 2.1 pc: add compat_props placeholder for 2.0 machine type i8259: don't abort when trying to use level sensitive irqs acpi: fix tables for no-hpet configuration acpi-build: properly decrement objects' reference counters acpi/pcihp.c: Rewrite acpi_pcihp_get_bsel using object_property_get_int Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/intc/i8259.c')
-rw-r--r--hw/intc/i8259.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/hw/intc/i8259.c b/hw/intc/i8259.c
index ec01393e4f..d0b0c52b97 100644
--- a/hw/intc/i8259.c
+++ b/hw/intc/i8259.c
@@ -265,7 +265,8 @@ static void pic_ioport_write(void *opaque, hwaddr addr64,
s->init4 = val & 1;
s->single_mode = val & 2;
if (val & 0x08) {
- hw_error("level sensitive irq not supported");
+ qemu_log_mask(LOG_UNIMP,
+ "i8259: level sensitive irq not supported\n");
}
} else if (val & 0x08) {
if (val & 0x04) {