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authorPeter Maydell <peter.maydell@linaro.org>2019-07-04 17:14:43 +0100
committerPeter Maydell <peter.maydell@linaro.org>2019-07-04 17:25:30 +0100
commit077d7449100d824a4e9230e349099399bde3b20f (patch)
treea560730cd75dc853b3380e7d89d1022ade5486c9 /hw/intc/aspeed_vic.c
parent7aab5a8c8bb525ea390b4ebc17ab82c0835cfdb6 (diff)
arm v8M: Forcibly clear negative-priority exceptions on deactivate
To prevent execution priority remaining negative if the guest returns from an NMI or HardFault with a corrupted IPSR, the v8M interrupt deactivation process forces the HardFault and NMI to inactive based on the current raw execution priority, even if the interrupt the guest is trying to deactivate is something else. In the pseudocode this is done in the Deactivate() function. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190617175317.27557-3-peter.maydell@linaro.org
Diffstat (limited to 'hw/intc/aspeed_vic.c')
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