diff options
| author | Fabian Aggeler <aggelerf@ethz.ch> | 2015-05-12 11:57:18 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2015-05-12 11:57:18 +0100 |
| commit | f9c6a7f1395c6d88a3bb1a0cb48811994709966e (patch) | |
| tree | 6ce9d8f972ed7aff094a9e0836bca36528ba9099 /hw/intc/armv7m_nvic.c | |
| parent | 7c0fa108d918ab818e49c4588ab290004d6b532e (diff) | |
hw/intc/arm_gic: Change behavior of EOIR writes
Grouping (GICv2) and Security Extensions change the behavior of EOIR
writes. Completing Group0 interrupts is only allowed from Secure state.
Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch>
Signed-off-by: Greg Bellows <greg.bellows@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1430502643-25909-13-git-send-email-peter.maydell@linaro.org
Message-id: 1429113742-8371-13-git-send-email-greg.bellows@linaro.org
[PMM: Rather than go to great lengths to ignore the UNPREDICTABLE case
of a Secure EOI of a Group1 (NS) irq with AckCtl == 0, we just let
it fall through; add a comment about it.]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/intc/armv7m_nvic.c')
| -rw-r--r-- | hw/intc/armv7m_nvic.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index a6567a378d..1bfff7530a 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -144,7 +144,7 @@ void armv7m_nvic_complete_irq(void *opaque, int irq) nvic_state *s = (nvic_state *)opaque; if (irq >= 16) irq += 16; - gic_complete_irq(&s->gic, 0, irq); + gic_complete_irq(&s->gic, 0, irq, MEMTXATTRS_UNSPECIFIED); } static uint32_t nvic_readl(nvic_state *s, uint32_t offset) |