diff options
| author | Christoffer Dall <christoffer.dall@linaro.org> | 2013-11-18 19:26:33 -0800 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2014-02-08 14:50:48 +0000 |
| commit | a9d477c4e3d614409a48d12f34624c2dd9f1ec2d (patch) | |
| tree | 71fe4a9c627ea3e375b1c428a527b9bf61ee2ea6 /hw/intc/arm_gic_common.c | |
| parent | a1b1d277cdaac98f25be249e7819aac781a35530 (diff) | |
arm_gic: Add GICC_APRn state to the GICState
The GICC_APRn registers are not currently supported by the ARM GIC v2.0
emulation. This patch adds the missing state.
Note that we also change the number of APRs to use a define GIC_NR_APRS
based on the maximum number of preemption levels. This patch also adds
RAZ/WI accessors for the four registers on the emulated CPU interface.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/intc/arm_gic_common.c')
| -rw-r--r-- | hw/intc/arm_gic_common.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/hw/intc/arm_gic_common.c b/hw/intc/arm_gic_common.c index d2d8ce1bb4..6d884eca3b 100644 --- a/hw/intc/arm_gic_common.c +++ b/hw/intc/arm_gic_common.c @@ -58,8 +58,8 @@ static const VMStateDescription vmstate_gic_irq_state = { static const VMStateDescription vmstate_gic = { .name = "arm_gic", - .version_id = 6, - .minimum_version_id = 6, + .version_id = 7, + .minimum_version_id = 7, .pre_save = gic_pre_save, .post_load = gic_post_load, .fields = (VMStateField[]) { @@ -78,6 +78,7 @@ static const VMStateDescription vmstate_gic = { VMSTATE_UINT16_ARRAY(current_pending, GICState, GIC_NCPU), VMSTATE_UINT8_ARRAY(bpr, GICState, GIC_NCPU), VMSTATE_UINT8_ARRAY(abpr, GICState, GIC_NCPU), + VMSTATE_UINT32_2DARRAY(apr, GICState, GIC_NR_APRS, GIC_NCPU), VMSTATE_END_OF_LIST() } }; |