diff options
| author | Peter Maydell <peter.maydell@linaro.org> | 2016-03-04 11:30:22 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2016-03-04 11:30:22 +0000 |
| commit | a55c910e0b18aee2f67b129f0046b53cb8c42f21 (patch) | |
| tree | 627482362a21b3711881f5be8f2e81caee8cc35e /hw/intc/arm_gic_common.c | |
| parent | 9776f636455b6f0d9c14dce112242ed653f954b4 (diff) | |
hw/intc/arm_gic.c: Implement GICv2 GICC_DIR
The GICv2 introduces a new CPU interface register GICC_DIR, which
allows an OS to split the "priority drop" and "deactivate interrupt"
parts of interrupt completion. Implement this register.
(Note that the register is at offset 0x1000 in the CPU interface,
which means it is on a different 4K page from all the other registers.)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com>
Message-id: 1456854176-7813-1-git-send-email-peter.maydell@linaro.org
Diffstat (limited to 'hw/intc/arm_gic_common.c')
| -rw-r--r-- | hw/intc/arm_gic_common.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/hw/intc/arm_gic_common.c b/hw/intc/arm_gic_common.c index ac8cf42eb8..707d00ded4 100644 --- a/hw/intc/arm_gic_common.c +++ b/hw/intc/arm_gic_common.c @@ -121,7 +121,7 @@ void gic_init_irqs_and_mmio(GICState *s, qemu_irq_handler handler, * neither it can use KVM. */ memory_region_init_io(&s->cpuiomem[0], OBJECT(s), ops ? &ops[1] : NULL, - s, "gic_cpu", s->revision == 2 ? 0x1000 : 0x100); + s, "gic_cpu", s->revision == 2 ? 0x2000 : 0x100); sysbus_init_mmio(sbd, &s->cpuiomem[0]); } } |