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authorPeter Maydell <peter.maydell@linaro.org>2018-08-24 13:17:31 +0100
committerPeter Maydell <peter.maydell@linaro.org>2018-08-24 13:17:31 +0100
commit7210918cade19b7c6f14c4403aac0fd381c07b1d (patch)
treed74d91f354be946190a5db4464b5529c4eeedf1b /hw/intc/arm_gic.c
parent323cd490845acf663159ca26e35cb977ad9b85a2 (diff)
hw/intc/arm_gic: Make per-cpu GICH memory regions 0x200 bytes large
Reduce the size of the per-cpu GICH memory regions from 0x1000 to 0x200. The registers only cover 0x200 bytes, and the Cortex-A15 wants to map them at a spacing of 0x200 bytes apart. Having the region be too large interferes with mapping them like that, so reduce it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Luc Michel <luc.michel@greensocs.com> Message-id: 20180821132811.17675-3-peter.maydell@linaro.org
Diffstat (limited to 'hw/intc/arm_gic.c')
-rw-r--r--hw/intc/arm_gic.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
index c1b35fc1ee..542b4b93ea 100644
--- a/hw/intc/arm_gic.c
+++ b/hw/intc/arm_gic.c
@@ -2084,7 +2084,7 @@ static void arm_gic_realize(DeviceState *dev, Error **errp)
for (i = 0; i < s->num_cpu; i++) {
memory_region_init_io(&s->vifaceiomem[i + 1], OBJECT(s),
&gic_viface_ops, &s->backref[i],
- "gic_viface", 0x1000);
+ "gic_viface", 0x200);
sysbus_init_mmio(sbd, &s->vifaceiomem[i + 1]);
}
}