diff options
| author | Christoffer Dall <christoffer.dall@linaro.org> | 2013-11-18 19:26:33 -0800 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2014-02-08 14:50:48 +0000 |
| commit | a9d477c4e3d614409a48d12f34624c2dd9f1ec2d (patch) | |
| tree | 71fe4a9c627ea3e375b1c428a527b9bf61ee2ea6 /hw/intc/arm_gic.c | |
| parent | a1b1d277cdaac98f25be249e7819aac781a35530 (diff) | |
arm_gic: Add GICC_APRn state to the GICState
The GICC_APRn registers are not currently supported by the ARM GIC v2.0
emulation. This patch adds the missing state.
Note that we also change the number of APRs to use a define GIC_NR_APRS
based on the maximum number of preemption levels. This patch also adds
RAZ/WI accessors for the four registers on the emulated CPU interface.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/intc/arm_gic.c')
| -rw-r--r-- | hw/intc/arm_gic.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index 5413a2482a..93eaa6b2fa 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -678,6 +678,8 @@ static uint32_t gic_cpu_read(GICState *s, int cpu, int offset) return s->current_pending[cpu]; case 0x1c: /* Aliased Binary Point */ return s->abpr[cpu]; + case 0xd0: case 0xd4: case 0xd8: case 0xdc: + return s->apr[(offset - 0xd0) / 4][cpu]; default: qemu_log_mask(LOG_GUEST_ERROR, "gic_cpu_read: Bad offset %x\n", (int)offset); @@ -705,6 +707,9 @@ static void gic_cpu_write(GICState *s, int cpu, int offset, uint32_t value) s->abpr[cpu] = (value & 0x7); } break; + case 0xd0: case 0xd4: case 0xd8: case 0xdc: + qemu_log_mask(LOG_UNIMP, "Writing APR not implemented\n"); + break; default: qemu_log_mask(LOG_GUEST_ERROR, "gic_cpu_write: Bad offset %x\n", (int)offset); |