diff options
| author | John Snow <jsnow@redhat.com> | 2018-06-08 13:17:38 -0400 |
|---|---|---|
| committer | John Snow <jsnow@redhat.com> | 2018-06-08 13:17:38 -0400 |
| commit | 467378baed0c1b3bfaa11eb97d1c231d1b0ed916 (patch) | |
| tree | a2c261aa0dd9d7cd4ee8c1455476a5fefee6999d /hw/ide | |
| parent | 9da8ac3203503195a9c602328ea25c73ed1ab55d (diff) | |
ahci: fix spacing damage on ahci_mem_write
Signed-off-by: John Snow <jsnow@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20180531222835.16558-14-jsnow@redhat.com
Signed-off-by: John Snow <jsnow@redhat.com>
Diffstat (limited to 'hw/ide')
| -rw-r--r-- | hw/ide/ahci.c | 47 |
1 files changed, 23 insertions, 24 deletions
diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c index b31eb84aaa..51c3e96c80 100644 --- a/hw/ide/ahci.c +++ b/hw/ide/ahci.c @@ -469,37 +469,36 @@ static void ahci_mem_write(void *opaque, hwaddr addr, if (addr < AHCI_GENERIC_HOST_CONTROL_REGS_MAX_ADDR) { switch (addr) { - case HOST_CAP: /* R/WO, RO */ - /* FIXME handle R/WO */ - break; - case HOST_CTL: /* R/W */ - if (val & HOST_CTL_RESET) { - ahci_reset(s); - } else { - s->control_regs.ghc = (val & 0x3) | HOST_CTL_AHCI_EN; - ahci_check_irq(s); - } - break; - case HOST_IRQ_STAT: /* R/WC, RO */ - s->control_regs.irqstatus &= ~val; + case HOST_CAP: /* R/WO, RO */ + /* FIXME handle R/WO */ + break; + case HOST_CTL: /* R/W */ + if (val & HOST_CTL_RESET) { + ahci_reset(s); + } else { + s->control_regs.ghc = (val & 0x3) | HOST_CTL_AHCI_EN; ahci_check_irq(s); - break; - case HOST_PORTS_IMPL: /* R/WO, RO */ - /* FIXME handle R/WO */ - break; - case HOST_VERSION: /* RO */ - /* FIXME report write? */ - break; - default: - trace_ahci_mem_write_unknown(s, size, addr, val); + } + break; + case HOST_IRQ_STAT: /* R/WC, RO */ + s->control_regs.irqstatus &= ~val; + ahci_check_irq(s); + break; + case HOST_PORTS_IMPL: /* R/WO, RO */ + /* FIXME handle R/WO */ + break; + case HOST_VERSION: /* RO */ + /* FIXME report write? */ + break; + default: + trace_ahci_mem_write_unknown(s, size, addr, val); } } else if ((addr >= AHCI_PORT_REGS_START_ADDR) && (addr < (AHCI_PORT_REGS_START_ADDR + - (s->ports * AHCI_PORT_ADDR_OFFSET_LEN)))) { + (s->ports * AHCI_PORT_ADDR_OFFSET_LEN)))) { ahci_port_write(s, (addr - AHCI_PORT_REGS_START_ADDR) >> 7, addr & AHCI_PORT_ADDR_OFFSET_MASK, val); } - } static const MemoryRegionOps ahci_mem_ops = { |