diff options
| author | Paolo Bonzini <pbonzini@redhat.com> | 2018-06-25 16:50:48 -0400 |
|---|---|---|
| committer | John Snow <jsnow@redhat.com> | 2018-06-25 16:50:48 -0400 |
| commit | ae79c2db150e17757ee1be080481be675a15ccea (patch) | |
| tree | e97e97af5a2e41126a88e51aff3b4a882b3b12df /hw/ide/ahci_internal.h | |
| parent | 35e238c9330669882487f9929e0aa97900431853 (diff) | |
ahci: fix FIS I bit and PIO Setup FIS interrupt
The "I" bit in PIO Setup and D2H FISes is exclusively a device concept
and the irqstatus register in the controller does not matter. The SATA
spec says when it should be one; for D2H FISes in practice it is always
set, while the PIO Setup FIS has several subcases that are documented in
the patch.
Also, the PIO Setup FIS interrupt is actually generated _after_ data
has been received.
Someone should probably spend some time reading the SATA specification and
figuring out the more obscure fields in the PIO Setup FIS, but this is enough
to fix SeaBIOS booting from ATAPI CD-ROMs over an AHCI controller.
Fixes: 956556e131e35f387ac482ad7b41151576fef057
Reported-by: Gerd Hoffmann <kraxel@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: John Snow <jsnow@redhat.com>
Message-id: 20180622165159.19863-1-pbonzini@redhat.com
[Minor edit to avoid ATAPI comment ambiguity. --js]
Signed-off-by: John Snow <jsnow@redhat.com>
Diffstat (limited to 'hw/ide/ahci_internal.h')
| -rw-r--r-- | hw/ide/ahci_internal.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/hw/ide/ahci_internal.h b/hw/ide/ahci_internal.h index 2953243929..9b7fa8fc7d 100644 --- a/hw/ide/ahci_internal.h +++ b/hw/ide/ahci_internal.h @@ -315,7 +315,7 @@ struct AHCIDevice { QEMUBH *check_bh; uint8_t *lst; uint8_t *res_fis; - bool done_atapi_packet; + bool done_first_drq; int32_t busy_slot; bool init_d2h_sent; AHCICmdHdr *cur_cmd; |