diff options
| author | Jan Kiszka <jan.kiszka@siemens.com> | 2009-05-02 00:29:37 +0200 |
|---|---|---|
| committer | Anthony Liguori <aliguori@us.ibm.com> | 2009-05-22 10:50:34 -0500 |
| commit | 8217606e6edb49591b4a6fd5a0d1229cebe470a9 (patch) | |
| tree | fff3d6f590833c0f894a6c7c300ab126b5259d95 /hw/ide.c | |
| parent | 93102fd6010c68320bc9a008c8cf70cb4a36d4b9 (diff) | |
Introduce reset notifier order
Add the parameter 'order' to qemu_register_reset and sort callbacks on
registration. On system reset, callbacks with lower order will be
invoked before those with higher order. Update all existing users to the
standard order 0.
Note: At least for x86, the existing users seem to assume that handlers
are called in their registration order. Therefore, the patch preserves
this property. If someone feels bored, (s)he could try to identify this
dependency and express it properly on callback registration.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Diffstat (limited to 'hw/ide.c')
| -rw-r--r-- | hw/ide.c | 8 |
1 files changed, 4 insertions, 4 deletions
@@ -3330,7 +3330,7 @@ void pci_cmd646_ide_init(PCIBus *bus, BlockDriverState **hd_table, ide_init2(&d->ide_if[2], hd_table[2], hd_table[3], irq[1]); register_savevm("ide", 0, 2, pci_ide_save, pci_ide_load, d); - qemu_register_reset(cmd646_reset, d); + qemu_register_reset(cmd646_reset, 0, d); cmd646_reset(d); } @@ -3373,7 +3373,7 @@ void pci_piix3_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn, pci_config_set_class(pci_conf, PCI_CLASS_STORAGE_IDE); pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type - qemu_register_reset(piix3_reset, d); + qemu_register_reset(piix3_reset, 0, d); piix3_reset(d); pci_register_io_region((PCIDevice *)d, 4, 0x10, @@ -3413,7 +3413,7 @@ void pci_piix4_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn, pci_config_set_class(pci_conf, PCI_CLASS_STORAGE_IDE); pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type - qemu_register_reset(piix3_reset, d); + qemu_register_reset(piix3_reset, 0, d); piix3_reset(d); pci_register_io_region((PCIDevice *)d, 4, 0x10, @@ -3754,7 +3754,7 @@ int pmac_ide_init (BlockDriverState **hd_table, qemu_irq irq, pmac_ide_memory = cpu_register_io_memory(0, pmac_ide_read, pmac_ide_write, d); register_savevm("ide", 0, 1, pmac_ide_save, pmac_ide_load, d); - qemu_register_reset(pmac_ide_reset, d); + qemu_register_reset(pmac_ide_reset, 0, d); pmac_ide_reset(d); return pmac_ide_memory; |