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authorBernhard Beschow <shentey@gmail.com>2023-02-13 18:30:30 +0100
committerPhilippe Mathieu-Daudé <philmd@linaro.org>2023-02-27 22:29:01 +0100
commite3e3a8ad1216faccd737f6bc06919deb366b0be3 (patch)
tree9437b5e3b1469442e0df33f619baeb2ba52afb75 /hw/i386
parentfb1856cb9b7cd81f45e1ee6ce079a4eea59314aa (diff)
hw/i386/ich9: Remove redundant GSI_NUM_PINS
Most code uses IOAPIC_NUM_PINS. The only place where GSI_NUM_PINS defines the size of an array is ICH9LPCState::gsi which needs to match IOAPIC_NUM_PINS. Remove GSI_NUM_PINS for consistency. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230213173033.98762-10-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Diffstat (limited to 'hw/i386')
-rw-r--r--hw/i386/pc.c6
-rw-r--r--hw/i386/pc_q35.c3
2 files changed, 5 insertions, 4 deletions
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index a7a2ededf9..d257545018 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -28,7 +28,7 @@
#include "hw/i386/pc.h"
#include "hw/char/serial.h"
#include "hw/char/parallel.h"
-#include "hw/i386/apic.h"
+#include "hw/i386/ioapic.h"
#include "hw/i386/topology.h"
#include "hw/i386/fw_cfg.h"
#include "hw/i386/vmport.h"
@@ -405,7 +405,7 @@ GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled)
if (kvm_ioapic_in_kernel()) {
kvm_pc_setup_irq_routing(pci_enabled);
}
- *irqs = qemu_allocate_irqs(gsi_handler, s, GSI_NUM_PINS);
+ *irqs = qemu_allocate_irqs(gsi_handler, s, IOAPIC_NUM_PINS);
return s;
}
@@ -1296,7 +1296,7 @@ void pc_basic_device_init(struct PCMachineState *pcms,
sysbus_realize_and_unref(SYS_BUS_DEVICE(hpet), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE);
- for (i = 0; i < GSI_NUM_PINS; i++) {
+ for (i = 0; i < IOAPIC_NUM_PINS; i++) {
sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]);
}
pit_isa_irq = -1;
diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
index 4508e8ac10..d35316878d 100644
--- a/hw/i386/pc_q35.c
+++ b/hw/i386/pc_q35.c
@@ -43,6 +43,7 @@
#include "hw/i386/ich9.h"
#include "hw/i386/amd_iommu.h"
#include "hw/i386/intel_iommu.h"
+#include "hw/i386/ioapic.h"
#include "hw/display/ramfb.h"
#include "hw/firmware/smbios.h"
#include "hw/ide/pci.h"
@@ -267,7 +268,7 @@ static void pc_q35_init(MachineState *machine)
gsi_state = pc_gsi_create(&x86ms->gsi, pcmc->pci_enabled);
lpc_dev = DEVICE(lpc);
- for (i = 0; i < GSI_NUM_PINS; i++) {
+ for (i = 0; i < IOAPIC_NUM_PINS; i++) {
qdev_connect_gpio_out_named(lpc_dev, ICH9_GPIO_GSI, i, x86ms->gsi[i]);
}
isa_bus = ISA_BUS(qdev_get_child_bus(lpc_dev, "isa.0"));