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authorBernhard Beschow <shentey@gmail.com>2023-02-13 18:30:23 +0100
committerPhilippe Mathieu-Daudé <philmd@linaro.org>2023-02-27 22:29:01 +0100
commit29a457cbbc90a9938f8ca3d6bf397e99b9559e58 (patch)
treebf732901e4496a8ee20e861ba0632836b8e7c6c2 /hw/i386/pc_q35.c
parentc288b6869a033986894607c8412bf23ec93f4d87 (diff)
hw/isa/lpc_ich9: Unexport PIRQ functions
No need to rely on the board to wire up the ICH9 PCI IRQs. All functions access private state of the LPC device which suggests that it should wire up the IRQs. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230213173033.98762-3-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Diffstat (limited to 'hw/i386/pc_q35.c')
-rw-r--r--hw/i386/pc_q35.c3
1 files changed, 0 insertions, 3 deletions
diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
index 66cd718b70..5dfaeeed5f 100644
--- a/hw/i386/pc_q35.c
+++ b/hw/i386/pc_q35.c
@@ -270,9 +270,6 @@ static void pc_q35_init(MachineState *machine)
for (i = 0; i < GSI_NUM_PINS; i++) {
qdev_connect_gpio_out_named(lpc_dev, ICH9_GPIO_GSI, i, x86ms->gsi[i]);
}
- pci_bus_irqs(host_bus, ich9_lpc_set_irq, ich9_lpc, ICH9_LPC_NB_PIRQS);
- pci_bus_map_irqs(host_bus, ich9_lpc_map_irq);
- pci_bus_set_route_irq_fn(host_bus, ich9_route_intx_pin_to_irq);
isa_bus = ich9_lpc->isa_bus;
if (x86ms->pic == ON_OFF_AUTO_ON || x86ms->pic == ON_OFF_AUTO_AUTO) {