aboutsummaryrefslogtreecommitdiff
path: root/hw/i2c
diff options
context:
space:
mode:
authorPeter Delevoryas <pdel@fb.com>2022-06-30 09:21:13 +0200
committerCédric Le Goater <clg@kaod.org>2022-06-30 09:21:13 +0200
commitb582b7a191f23c3f862c3b3aef96d6136508c07f (patch)
tree302168a5335701a24d57a157129999857bb4342d /hw/i2c
parentceb3ff0e802bf7e373b1dbcff51541eefff25513 (diff)
hw/i2c/aspeed: Fix DMA len write-enable bit handling
I noticed i2c rx transfers were getting shortened to "1" on Zephyr. It seems to be because the Zephyr i2c driver sets the RX DMA len with the RX field write-enable bit set (bit 31) to avoid a read-modify-write. [1] /* 0x1C : I2CM Master DMA Transfer Length Register */ I think we should be checking the write-enable bits on the incoming value, not checking the register array. I'm not sure we're even writing the write-enable bits to the register array, actually. [1] https://github.com/AspeedTech-BMC/zephyr/blob/db3dbcc9c52e67a47180890ac938ed380b33f91c/drivers/i2c/i2c_aspeed.c#L145-L148 Fixes: ba2cccd64e90f34 ("aspeed: i2c: Add new mode support") Signed-off-by: Peter Delevoryas <pdel@fb.com> Message-Id: <20220630045133.32251-3-me@pjd.dev> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
Diffstat (limited to 'hw/i2c')
-rw-r--r--hw/i2c/aspeed_i2c.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/hw/i2c/aspeed_i2c.c b/hw/i2c/aspeed_i2c.c
index 6429ab1874..4e32b147ec 100644
--- a/hw/i2c/aspeed_i2c.c
+++ b/hw/i2c/aspeed_i2c.c
@@ -644,18 +644,18 @@ static void aspeed_i2c_bus_new_write(AspeedI2CBus *bus, hwaddr offset,
RX_BUF_LEN) + 1;
break;
case A_I2CM_DMA_LEN:
- w1t = ARRAY_FIELD_EX32(bus->regs, I2CM_DMA_LEN, RX_BUF_LEN_W1T) ||
- ARRAY_FIELD_EX32(bus->regs, I2CM_DMA_LEN, TX_BUF_LEN_W1T);
+ w1t = FIELD_EX32(value, I2CM_DMA_LEN, RX_BUF_LEN_W1T) ||
+ FIELD_EX32(value, I2CM_DMA_LEN, TX_BUF_LEN_W1T);
/* If none of the w1t bits are set, just write to the reg as normal. */
if (!w1t) {
bus->regs[R_I2CM_DMA_LEN] = value;
break;
}
- if (ARRAY_FIELD_EX32(bus->regs, I2CM_DMA_LEN, RX_BUF_LEN_W1T)) {
+ if (FIELD_EX32(value, I2CM_DMA_LEN, RX_BUF_LEN_W1T)) {
ARRAY_FIELD_DP32(bus->regs, I2CM_DMA_LEN, RX_BUF_LEN,
FIELD_EX32(value, I2CM_DMA_LEN, RX_BUF_LEN));
}
- if (ARRAY_FIELD_EX32(bus->regs, I2CM_DMA_LEN, TX_BUF_LEN_W1T)) {
+ if (FIELD_EX32(value, I2CM_DMA_LEN, TX_BUF_LEN_W1T)) {
ARRAY_FIELD_DP32(bus->regs, I2CM_DMA_LEN, TX_BUF_LEN,
FIELD_EX32(value, I2CM_DMA_LEN, TX_BUF_LEN));
}