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authorths <ths@c046a42c-6fe2-441c-8c8c-71466251a162>2007-01-24 01:47:51 +0000
committerths <ths@c046a42c-6fe2-441c-8c8c-71466251a162>2007-01-24 01:47:51 +0000
commit4de9b249d37c1b382cc3e5a21fad1b4a11cec2fa (patch)
tree3991d58b09108b5c18a4388b2c2a8b6cb8f57142 /hw/gt64xxx.c
parent30c4bbace19e802979009cc5c16fb4e14dc6bda6 (diff)
Reworking MIPS interrupt handling, by Aurelien Jarno.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2350 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'hw/gt64xxx.c')
-rw-r--r--hw/gt64xxx.c5
1 files changed, 3 insertions, 2 deletions
diff --git a/hw/gt64xxx.c b/hw/gt64xxx.c
index f3ff613811..84e041fcfc 100644
--- a/hw/gt64xxx.c
+++ b/hw/gt64xxx.c
@@ -1,7 +1,7 @@
/*
* QEMU GT64120 PCI host
*
- * Copyright (c) 2006 Aurelien Jarno
+ * Copyright (c) 2006,2007 Aurelien Jarno
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -433,7 +433,8 @@ static uint32_t gt64120_readl (void *opaque,
val = s->regs[saddr];
break;
case GT_PCI0_IACK:
- val = pic_intack_read(isa_pic);
+ /* Read the IRQ number */
+ val = pic_read_irq(isa_pic);
break;
/* SDRAM Parameters */