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authoraliguori <aliguori@c046a42c-6fe2-441c-8c8c-71466251a162>2008-12-09 20:09:57 +0000
committeraliguori <aliguori@c046a42c-6fe2-441c-8c8c-71466251a162>2008-12-09 20:09:57 +0000
commitf65ed4c1529f29a7d62d6733eaa50bed24a4b2ed (patch)
tree1d0351afc0542f8f709f9ed7f6a445474b137a9e /hw/e1000.c
parentd85dc283fa87353be10b11b463196d10eb49ca41 (diff)
KVM: Coalesced MMIO support
MMIO exits are more expensive in KVM or Xen than in QEMU because they involve, at least, privilege transitions. However, MMIO write operations can be effectively batched if those writes do not have side effects. Good examples of this include VGA pixel operations when in a planar mode. As it turns out, we can get a nice boost in other areas too. Laurent mentioned a 9.7% performance boost in iperf with the coalesced MMIO changes for the e1000 when he originally posted this work for KVM. Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5961 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'hw/e1000.c')
-rw-r--r--hw/e1000.c12
1 files changed, 12 insertions, 0 deletions
diff --git a/hw/e1000.c b/hw/e1000.c
index f07936fdc1..67a062a318 100644
--- a/hw/e1000.c
+++ b/hw/e1000.c
@@ -1001,10 +1001,22 @@ e1000_mmio_map(PCIDevice *pci_dev, int region_num,
uint32_t addr, uint32_t size, int type)
{
E1000State *d = (E1000State *)pci_dev;
+ int i;
+ const uint32_t excluded_regs[] = {
+ E1000_MDIC, E1000_ICR, E1000_ICS, E1000_IMS,
+ E1000_IMC, E1000_TCTL, E1000_TDT, PNPMMIO_SIZE
+ };
+
DBGOUT(MMIO, "e1000_mmio_map addr=0x%08x 0x%08x\n", addr, size);
cpu_register_physical_memory(addr, PNPMMIO_SIZE, d->mmio_index);
+ qemu_register_coalesced_mmio(addr, excluded_regs[0]);
+
+ for (i = 0; excluded_regs[i] != PNPMMIO_SIZE; i++)
+ qemu_register_coalesced_mmio(addr + excluded_regs[i] + 4,
+ excluded_regs[i + 1] -
+ excluded_regs[i] - 4);
}
void