diff options
| author | Philippe Mathieu-Daudé <philmd@redhat.com> | 2020-09-10 09:01:28 +0200 |
|---|---|---|
| committer | Paolo Bonzini <pbonzini@redhat.com> | 2020-12-10 12:15:04 -0500 |
| commit | 484f86de7e00ec2096d2d12388caf8009aaae3eb (patch) | |
| tree | 6eeb7c2f6aa0e318faa7a65200587682f76cc0dc /hw/dma/xilinx_axidma.c | |
| parent | cfbef3f4eb3816099bf573bdb238e4aad8803c4c (diff) | |
hw/dma/xilinx_axidma: Rename StreamSlave as StreamSink
In order to use inclusive terminology, rename 'slave stream'
as 'sink stream'.
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-Id: <20200910070131.435543-4-philmd@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'hw/dma/xilinx_axidma.c')
| -rw-r--r-- | hw/dma/xilinx_axidma.c | 26 |
1 files changed, 13 insertions, 13 deletions
diff --git a/hw/dma/xilinx_axidma.c b/hw/dma/xilinx_axidma.c index 306da46699..bc383f53cc 100644 --- a/hw/dma/xilinx_axidma.c +++ b/hw/dma/xilinx_axidma.c @@ -45,11 +45,11 @@ OBJECT_DECLARE_SIMPLE_TYPE(XilinxAXIDMA, XILINX_AXI_DMA) -typedef struct XilinxAXIDMAStreamSlave XilinxAXIDMAStreamSlave; -DECLARE_INSTANCE_CHECKER(XilinxAXIDMAStreamSlave, XILINX_AXI_DMA_DATA_STREAM, +typedef struct XilinxAXIDMAStreamSink XilinxAXIDMAStreamSink; +DECLARE_INSTANCE_CHECKER(XilinxAXIDMAStreamSink, XILINX_AXI_DMA_DATA_STREAM, TYPE_XILINX_AXI_DMA_DATA_STREAM) -DECLARE_INSTANCE_CHECKER(XilinxAXIDMAStreamSlave, XILINX_AXI_DMA_CONTROL_STREAM, +DECLARE_INSTANCE_CHECKER(XilinxAXIDMAStreamSink, XILINX_AXI_DMA_CONTROL_STREAM, TYPE_XILINX_AXI_DMA_CONTROL_STREAM) #define R_DMACR (0x00 / 4) @@ -115,7 +115,7 @@ struct Stream { unsigned char txbuf[16 * 1024]; }; -struct XilinxAXIDMAStreamSlave { +struct XilinxAXIDMAStreamSink { Object parent; struct XilinxAXIDMA *dma; @@ -130,8 +130,8 @@ struct XilinxAXIDMA { uint32_t freqhz; StreamSink *tx_data_dev; StreamSink *tx_control_dev; - XilinxAXIDMAStreamSlave rx_data_dev; - XilinxAXIDMAStreamSlave rx_control_dev; + XilinxAXIDMAStreamSink rx_data_dev; + XilinxAXIDMAStreamSink rx_control_dev; struct Stream streams[2]; @@ -387,7 +387,7 @@ static size_t xilinx_axidma_control_stream_push(StreamSink *obj, unsigned char *buf, size_t len, bool eop) { - XilinxAXIDMAStreamSlave *cs = XILINX_AXI_DMA_CONTROL_STREAM(obj); + XilinxAXIDMAStreamSink *cs = XILINX_AXI_DMA_CONTROL_STREAM(obj); struct Stream *s = &cs->dma->streams[1]; if (len != CONTROL_PAYLOAD_SIZE) { @@ -404,7 +404,7 @@ xilinx_axidma_data_stream_can_push(StreamSink *obj, StreamCanPushNotifyFn notify, void *notify_opaque) { - XilinxAXIDMAStreamSlave *ds = XILINX_AXI_DMA_DATA_STREAM(obj); + XilinxAXIDMAStreamSink *ds = XILINX_AXI_DMA_DATA_STREAM(obj); struct Stream *s = &ds->dma->streams[1]; if (!stream_running(s) || stream_idle(s)) { @@ -420,7 +420,7 @@ static size_t xilinx_axidma_data_stream_push(StreamSink *obj, unsigned char *buf, size_t len, bool eop) { - XilinxAXIDMAStreamSlave *ds = XILINX_AXI_DMA_DATA_STREAM(obj); + XilinxAXIDMAStreamSink *ds = XILINX_AXI_DMA_DATA_STREAM(obj); struct Stream *s = &ds->dma->streams[1]; size_t ret; @@ -531,8 +531,8 @@ static const MemoryRegionOps axidma_ops = { static void xilinx_axidma_realize(DeviceState *dev, Error **errp) { XilinxAXIDMA *s = XILINX_AXI_DMA(dev); - XilinxAXIDMAStreamSlave *ds = XILINX_AXI_DMA_DATA_STREAM(&s->rx_data_dev); - XilinxAXIDMAStreamSlave *cs = XILINX_AXI_DMA_CONTROL_STREAM( + XilinxAXIDMAStreamSink *ds = XILINX_AXI_DMA_DATA_STREAM(&s->rx_data_dev); + XilinxAXIDMAStreamSink *cs = XILINX_AXI_DMA_CONTROL_STREAM( &s->rx_control_dev); int i; @@ -631,7 +631,7 @@ static const TypeInfo axidma_info = { static const TypeInfo xilinx_axidma_data_stream_info = { .name = TYPE_XILINX_AXI_DMA_DATA_STREAM, .parent = TYPE_OBJECT, - .instance_size = sizeof(XilinxAXIDMAStreamSlave), + .instance_size = sizeof(XilinxAXIDMAStreamSink), .class_init = xilinx_axidma_stream_class_init, .class_data = &xilinx_axidma_data_stream_class, .interfaces = (InterfaceInfo[]) { @@ -643,7 +643,7 @@ static const TypeInfo xilinx_axidma_data_stream_info = { static const TypeInfo xilinx_axidma_control_stream_info = { .name = TYPE_XILINX_AXI_DMA_CONTROL_STREAM, .parent = TYPE_OBJECT, - .instance_size = sizeof(XilinxAXIDMAStreamSlave), + .instance_size = sizeof(XilinxAXIDMAStreamSink), .class_init = xilinx_axidma_stream_class_init, .class_data = &xilinx_axidma_control_stream_class, .interfaces = (InterfaceInfo[]) { |