diff options
| author | Eduardo Habkost <ehabkost@redhat.com> | 2020-08-31 17:07:33 -0400 |
|---|---|---|
| committer | Eduardo Habkost <ehabkost@redhat.com> | 2020-09-09 09:27:09 -0400 |
| commit | 8110fa1d94f2997badc2af39231a1d279c5bb1ee (patch) | |
| tree | 6bff28c7907dfb0cbb367ca113f4d02ea03f3a51 /hw/dma/xilinx_axidma.c | |
| parent | db1015e92e04835c9eb50c29625fe566d1202dbd (diff) | |
Use DECLARE_*CHECKER* macros
Generated using:
$ ./scripts/codeconverter/converter.py -i \
--pattern=TypeCheckMacro $(git grep -l '' -- '*.[ch]')
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Reviewed-by: Juan Quintela <quintela@redhat.com>
Message-Id: <20200831210740.126168-12-ehabkost@redhat.com>
Reviewed-by: Juan Quintela <quintela@redhat.com>
Message-Id: <20200831210740.126168-13-ehabkost@redhat.com>
Message-Id: <20200831210740.126168-14-ehabkost@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Diffstat (limited to 'hw/dma/xilinx_axidma.c')
| -rw-r--r-- | hw/dma/xilinx_axidma.c | 14 |
1 files changed, 6 insertions, 8 deletions
diff --git a/hw/dma/xilinx_axidma.c b/hw/dma/xilinx_axidma.c index 6d48fea8fe..f313453495 100644 --- a/hw/dma/xilinx_axidma.c +++ b/hw/dma/xilinx_axidma.c @@ -44,17 +44,15 @@ #define TYPE_XILINX_AXI_DMA_CONTROL_STREAM "xilinx-axi-dma-control-stream" typedef struct XilinxAXIDMA XilinxAXIDMA; -#define XILINX_AXI_DMA(obj) \ - OBJECT_CHECK(XilinxAXIDMA, (obj), TYPE_XILINX_AXI_DMA) +DECLARE_INSTANCE_CHECKER(XilinxAXIDMA, XILINX_AXI_DMA, + TYPE_XILINX_AXI_DMA) typedef struct XilinxAXIDMAStreamSlave XilinxAXIDMAStreamSlave; -#define XILINX_AXI_DMA_DATA_STREAM(obj) \ - OBJECT_CHECK(XilinxAXIDMAStreamSlave, (obj),\ - TYPE_XILINX_AXI_DMA_DATA_STREAM) +DECLARE_INSTANCE_CHECKER(XilinxAXIDMAStreamSlave, XILINX_AXI_DMA_DATA_STREAM, + TYPE_XILINX_AXI_DMA_DATA_STREAM) -#define XILINX_AXI_DMA_CONTROL_STREAM(obj) \ - OBJECT_CHECK(XilinxAXIDMAStreamSlave, (obj),\ - TYPE_XILINX_AXI_DMA_CONTROL_STREAM) +DECLARE_INSTANCE_CHECKER(XilinxAXIDMAStreamSlave, XILINX_AXI_DMA_CONTROL_STREAM, + TYPE_XILINX_AXI_DMA_CONTROL_STREAM) #define R_DMACR (0x00 / 4) #define R_DMASR (0x04 / 4) |