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| author | Bin Meng <bin.meng@windriver.com> | 2021-07-06 18:26:16 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2021-07-15 08:56:00 +1000 |
| commit | 074ca702e64dcea15c9c3b2c1931351cf397debe (patch) | |
| tree | f5523a7dc87081014d93d44b69f23da9369bd192 /hw/display/qxl-logger.c | |
| parent | 6165dcb55f0ab4b2a241e49859ce6262157887e7 (diff) | |
hw/riscv: sifive_u: Correct the CLINT timebase frequency
At present the CLINT timebase frequency is set to 10MHz on sifive_u,
but on the real hardware the timebase frequency is 1Mhz.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210706102616.1922469-1-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/display/qxl-logger.c')
0 files changed, 0 insertions, 0 deletions