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authorAnthony Liguori <anthony@codemonkey.ws>2013-09-03 12:33:32 -0500
committerAnthony Liguori <anthony@codemonkey.ws>2013-09-03 12:33:32 -0500
commitaaa6a40194e9f204cb853f64ef3c1e170bb014e8 (patch)
treed2cfe475e7bcdafdf50fa2cca72a1a0050794af8 /hw/cpu
parentbb7d4d82b63bbde06c5584f94bfd9ba3b3e5ff3f (diff)
parent5e891bf8fd509c4d83cb95d352d88effb20720b1 (diff)
Merge remote-tracking branch 'afaerber/tags/qom-cpu-for-anthony' into staging
QOM CPUState refactorings / X86CPU * Conversion of global CPU list to QTAILQ - preparing for CPU hot-unplug * Document X86CPU magic numbers for CPUID cache info # gpg: Signature made Tue 03 Sep 2013 10:59:22 AM CDT using RSA key ID 3E7E013F # gpg: Can't check signature: public key not found # By Andreas Färber (3) and Eduardo Habkost (1) # Via Andreas Färber * afaerber/tags/qom-cpu-for-anthony: target-i386: Use #defines instead of magic numbers for CPUID cache info cpu: Replace qemu_for_each_cpu() cpu: Use QTAILQ for CPU list a15mpcore: Use qemu_get_cpu() for generic timers
Diffstat (limited to 'hw/cpu')
-rw-r--r--hw/cpu/a15mpcore.c5
1 files changed, 2 insertions, 3 deletions
diff --git a/hw/cpu/a15mpcore.c b/hw/cpu/a15mpcore.c
index af182da4ee..9abba67632 100644
--- a/hw/cpu/a15mpcore.c
+++ b/hw/cpu/a15mpcore.c
@@ -50,7 +50,6 @@ static int a15mp_priv_init(SysBusDevice *dev)
SysBusDevice *busdev;
const char *gictype = "arm_gic";
int i;
- CPUState *cpu;
if (kvm_irqchip_in_kernel()) {
gictype = "kvm-arm-gic";
@@ -72,8 +71,8 @@ static int a15mp_priv_init(SysBusDevice *dev)
/* Wire the outputs from each CPU's generic timer to the
* appropriate GIC PPI inputs
*/
- for (i = 0, cpu = first_cpu; i < s->num_cpu; i++, cpu = cpu->next_cpu) {
- DeviceState *cpudev = DEVICE(cpu);
+ for (i = 0; i < s->num_cpu; i++) {
+ DeviceState *cpudev = DEVICE(qemu_get_cpu(i));
int ppibase = s->num_irq - 32 + i * 32;
/* physical timer; we wire it up to the non-secure timer's ID,
* since a real A15 always has TrustZone but QEMU doesn't.