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authorPeter Maydell <peter.maydell@linaro.org>2022-05-12 16:14:56 +0100
committerPeter Maydell <peter.maydell@linaro.org>2022-05-19 16:19:02 +0100
commit39f29e599355f9512482b67624e7a6c9000c5ddd (patch)
treedd77f822d119d5803f253339394048c47f0a4d46 /hw/core/machine.c
parent84597ff39484ec171567c7c80061100eb4a6c331 (diff)
hw/intc/arm_gicv3: Use correct number of priority bits for the CPU
Make the GICv3 set its number of bits of physical priority from the implementation-specific value provided in the CPU state struct, in the same way we already do for virtual priority bits. Because this would be a migration compatibility break, we provide a property force-8-bit-prio which is enabled for 7.0 and earlier versioned board models to retain the legacy "always use 8 bits" behaviour. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220512151457.3899052-6-peter.maydell@linaro.org Message-id: 20220506162129.2896966-5-peter.maydell@linaro.org
Diffstat (limited to 'hw/core/machine.c')
-rw-r--r--hw/core/machine.c4
1 files changed, 3 insertions, 1 deletions
diff --git a/hw/core/machine.c b/hw/core/machine.c
index b03d9192ba..bb0dc8f6a9 100644
--- a/hw/core/machine.c
+++ b/hw/core/machine.c
@@ -41,7 +41,9 @@
#include "hw/virtio/virtio-pci.h"
#include "qom/object_interfaces.h"
-GlobalProperty hw_compat_7_0[] = {};
+GlobalProperty hw_compat_7_0[] = {
+ { "arm-gicv3-common", "force-8-bit-prio", "on" },
+};
const size_t hw_compat_7_0_len = G_N_ELEMENTS(hw_compat_7_0);
GlobalProperty hw_compat_6_2[] = {