diff options
author | bellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162> | 2005-01-26 19:50:16 +0000 |
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committer | bellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162> | 2005-01-26 19:50:16 +0000 |
commit | 0b74ed78ef3879af7f32bb31693d9e3e71d4b5dd (patch) | |
tree | 11ad120c751788b2818e23df480032db3297ff33 /hw/cirrus_vga.c | |
parent | f51589dad53ff431d827f1326b5313b81488e0dc (diff) |
mode 4 and 5 write fix (Magnus Damn)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1241 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'hw/cirrus_vga.c')
-rw-r--r-- | hw/cirrus_vga.c | 16 |
1 files changed, 9 insertions, 7 deletions
diff --git a/hw/cirrus_vga.c b/hw/cirrus_vga.c index d3eba4a348..4b92b4090d 100644 --- a/hw/cirrus_vga.c +++ b/hw/cirrus_vga.c @@ -790,7 +790,7 @@ static void cirrus_bitblt_start(CirrusVGAState * s) blt_rop = s->gr[0x32]; #ifdef DEBUG_BITBLT - printf("rop=0x%02x mode=0x%02x modeext=0x%02x w=%d h=%d dpitch=%d spicth=%d daddr=0x%08x saddr=0x%08x writemask=0x%02x\n", + printf("rop=0x%02x mode=0x%02x modeext=0x%02x w=%d h=%d dpitch=%d spitch=%d daddr=0x%08x saddr=0x%08x writemask=0x%02x\n", blt_rop, s->cirrus_blt_mode, s->cirrus_blt_modeext, @@ -1780,11 +1780,12 @@ static void cirrus_mem_writeb_mode4and5_8bpp(CirrusVGAState * s, dst = s->vram_ptr + offset; for (x = 0; x < 8; x++) { if (val & 0x80) { - *dst++ = s->cirrus_shadow_gr1; + *dst = s->cirrus_shadow_gr1; } else if (mode == 5) { - *dst++ = s->cirrus_shadow_gr0; + *dst = s->cirrus_shadow_gr0; } val <<= 1; + dst++; } cpu_physical_memory_set_dirty(s->vram_offset + offset); cpu_physical_memory_set_dirty(s->vram_offset + offset + 7); @@ -1802,13 +1803,14 @@ static void cirrus_mem_writeb_mode4and5_16bpp(CirrusVGAState * s, dst = s->vram_ptr + offset; for (x = 0; x < 8; x++) { if (val & 0x80) { - *dst++ = s->cirrus_shadow_gr1; - *dst++ = s->gr[0x11]; + *dst = s->cirrus_shadow_gr1; + *(dst + 1) = s->gr[0x11]; } else if (mode == 5) { - *dst++ = s->cirrus_shadow_gr0; - *dst++ = s->gr[0x10]; + *dst = s->cirrus_shadow_gr0; + *(dst + 1) = s->gr[0x10]; } val <<= 1; + dst += 2; } cpu_physical_memory_set_dirty(s->vram_offset + offset); cpu_physical_memory_set_dirty(s->vram_offset + offset + 15); |