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authorBALATON Zoltan <balaton@eik.bme.hu>2021-10-29 23:02:09 +0200
committerPhilippe Mathieu-Daudé <f4bug@amsat.org>2021-10-30 11:46:40 +0200
commitac3c9e74c1ee1071e5be692a611c5ee261b9b581 (patch)
treec64ce8e8b2af3087b414f16a6b16ad916d5d85e1 /hw/char
parentf94bff1337ff525e2ff458b8e4cd57f9561acde3 (diff)
hw/sh4: Coding style: Add missing braces
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Yoshinori Sato <ysato@users.sourceforge.jp> Message-Id: <b53a8cbcf57207fbd6408db1007b3e82008d60f7.1635541329.git.balaton@eik.bme.hu> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Diffstat (limited to 'hw/char')
-rw-r--r--hw/char/sh_serial.c48
1 files changed, 32 insertions, 16 deletions
diff --git a/hw/char/sh_serial.c b/hw/char/sh_serial.c
index 3fdb9f9a99..1b1e6a6a04 100644
--- a/hw/char/sh_serial.c
+++ b/hw/char/sh_serial.c
@@ -103,8 +103,9 @@ static void sh_serial_write(void *opaque, hwaddr offs,
case 0x08: /* SCR */
/* TODO : For SH7751, SCIF mask should be 0xfb. */
s->scr = val & ((s->feat & SH_SERIAL_FEAT_SCIF) ? 0xfa : 0xff);
- if (!(val & (1 << 5)))
+ if (!(val & (1 << 5))) {
s->flags |= SH_SERIAL_FLAG_TEND;
+ }
if ((s->feat & SH_SERIAL_FEAT_SCIF) && s->txi) {
qemu_set_irq(s->txi, val & (1 << 7));
}
@@ -133,16 +134,21 @@ static void sh_serial_write(void *opaque, hwaddr offs,
if (s->feat & SH_SERIAL_FEAT_SCIF) {
switch (offs) {
case 0x10: /* FSR */
- if (!(val & (1 << 6)))
+ if (!(val & (1 << 6))) {
s->flags &= ~SH_SERIAL_FLAG_TEND;
- if (!(val & (1 << 5)))
+ }
+ if (!(val & (1 << 5))) {
s->flags &= ~SH_SERIAL_FLAG_TDE;
- if (!(val & (1 << 4)))
+ }
+ if (!(val & (1 << 4))) {
s->flags &= ~SH_SERIAL_FLAG_BRK;
- if (!(val & (1 << 1)))
+ }
+ if (!(val & (1 << 1))) {
s->flags &= ~SH_SERIAL_FLAG_RDF;
- if (!(val & (1 << 0)))
+ }
+ if (!(val & (1 << 0))) {
s->flags &= ~SH_SERIAL_FLAG_DR;
+ }
if (!(val & (1 << 1)) || !(val & (1 << 0))) {
if (s->rxi) {
@@ -231,29 +237,37 @@ static uint64_t sh_serial_read(void *opaque, hwaddr offs,
break;
case 0x10: /* FSR */
ret = 0;
- if (s->flags & SH_SERIAL_FLAG_TEND)
+ if (s->flags & SH_SERIAL_FLAG_TEND) {
ret |= (1 << 6);
- if (s->flags & SH_SERIAL_FLAG_TDE)
+ }
+ if (s->flags & SH_SERIAL_FLAG_TDE) {
ret |= (1 << 5);
- if (s->flags & SH_SERIAL_FLAG_BRK)
+ }
+ if (s->flags & SH_SERIAL_FLAG_BRK) {
ret |= (1 << 4);
- if (s->flags & SH_SERIAL_FLAG_RDF)
+ }
+ if (s->flags & SH_SERIAL_FLAG_RDF) {
ret |= (1 << 1);
- if (s->flags & SH_SERIAL_FLAG_DR)
+ }
+ if (s->flags & SH_SERIAL_FLAG_DR) {
ret |= (1 << 0);
+ }
- if (s->scr & (1 << 5))
+ if (s->scr & (1 << 5)) {
s->flags |= SH_SERIAL_FLAG_TDE | SH_SERIAL_FLAG_TEND;
+ }
break;
case 0x14:
if (s->rx_cnt > 0) {
ret = s->rx_fifo[s->rx_tail++];
s->rx_cnt--;
- if (s->rx_tail == SH_RX_FIFO_LENGTH)
+ if (s->rx_tail == SH_RX_FIFO_LENGTH) {
s->rx_tail = 0;
- if (s->rx_cnt < s->rtrg)
+ }
+ if (s->rx_cnt < s->rtrg) {
s->flags &= ~SH_SERIAL_FLAG_RDF;
+ }
}
break;
case 0x18:
@@ -308,8 +322,9 @@ static int sh_serial_can_receive(sh_serial_state *s)
static void sh_serial_receive_break(sh_serial_state *s)
{
- if (s->feat & SH_SERIAL_FEAT_SCIF)
+ if (s->feat & SH_SERIAL_FEAT_SCIF) {
s->sr |= (1 << 4);
+ }
}
static int sh_serial_can_receive1(void *opaque)
@@ -361,8 +376,9 @@ static void sh_serial_receive1(void *opaque, const uint8_t *buf, int size)
static void sh_serial_event(void *opaque, QEMUChrEvent event)
{
sh_serial_state *s = opaque;
- if (event == CHR_EVENT_BREAK)
+ if (event == CHR_EVENT_BREAK) {
sh_serial_receive_break(s);
+ }
}
static const MemoryRegionOps sh_serial_ops = {