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authorMarc-André Lureau <marcandre.lureau@redhat.com>2016-10-22 12:52:55 +0300
committerPaolo Bonzini <pbonzini@redhat.com>2016-10-24 15:27:21 +0200
commit5345fdb4467816c44f6752b3a1f4e73aa25919f9 (patch)
tree9930cf4370d2325d113408f7b314cd77aa43f8a3 /hw/char/cadence_uart.c
parentfbf3cc3a67a7131e258764aa1f19d5324e9e9f7a (diff)
char: use qemu_chr_fe* functions with CharBackend argument
This also switches from qemu_chr_add_handlers() to qemu_chr_fe_set_handlers(). Note that qemu_chr_fe_set_handlers() now takes the focus when fe_open (qemu_chr_add_handlers() did take the focus) Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20161022095318.17775-16-marcandre.lureau@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'hw/char/cadence_uart.c')
-rw-r--r--hw/char/cadence_uart.c20
1 files changed, 10 insertions, 10 deletions
diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c
index c02723502c..4459b2d6af 100644
--- a/hw/char/cadence_uart.c
+++ b/hw/char/cadence_uart.c
@@ -143,7 +143,7 @@ static void uart_rx_reset(CadenceUARTState *s)
s->rx_wpos = 0;
s->rx_count = 0;
if (s->chr.chr) {
- qemu_chr_fe_accept_input(s->chr.chr);
+ qemu_chr_fe_accept_input(&s->chr);
}
}
@@ -157,8 +157,8 @@ static void uart_send_breaks(CadenceUARTState *s)
int break_enabled = 1;
if (s->chr.chr) {
- qemu_chr_fe_ioctl(s->chr.chr, CHR_IOCTL_SERIAL_SET_BREAK,
- &break_enabled);
+ qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_BREAK,
+ &break_enabled);
}
}
@@ -211,7 +211,7 @@ static void uart_parameters_setup(CadenceUARTState *s)
packet_size += ssp.data_bits + ssp.stop_bits;
s->char_tx_time = (NANOSECONDS_PER_SECOND / ssp.speed) * packet_size;
if (s->chr.chr) {
- qemu_chr_fe_ioctl(s->chr.chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
+ qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
}
}
@@ -278,7 +278,7 @@ static gboolean cadence_uart_xmit(GIOChannel *chan, GIOCondition cond,
int ret;
/* instant drain the fifo when there's no back-end */
- if (!s->chr.chr) {
+ if (!qemu_chr_fe_get_driver(&s->chr)) {
s->tx_count = 0;
return FALSE;
}
@@ -287,7 +287,7 @@ static gboolean cadence_uart_xmit(GIOChannel *chan, GIOCondition cond,
return FALSE;
}
- ret = qemu_chr_fe_write(s->chr.chr, s->tx_fifo, s->tx_count);
+ ret = qemu_chr_fe_write(&s->chr, s->tx_fifo, s->tx_count);
if (ret >= 0) {
s->tx_count -= ret;
@@ -295,7 +295,7 @@ static gboolean cadence_uart_xmit(GIOChannel *chan, GIOCondition cond,
}
if (s->tx_count) {
- guint r = qemu_chr_fe_add_watch(s->chr.chr, G_IO_OUT | G_IO_HUP,
+ guint r = qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP,
cadence_uart_xmit, s);
if (!r) {
s->tx_count = 0;
@@ -369,7 +369,7 @@ static void uart_read_rx_fifo(CadenceUARTState *s, uint32_t *c)
s->rx_count--;
if (s->chr.chr) {
- qemu_chr_fe_accept_input(s->chr.chr);
+ qemu_chr_fe_accept_input(&s->chr);
}
} else {
*c = 0;
@@ -475,8 +475,8 @@ static void cadence_uart_realize(DeviceState *dev, Error **errp)
fifo_trigger_update, s);
if (s->chr.chr) {
- qemu_chr_add_handlers(s->chr.chr, uart_can_receive, uart_receive,
- uart_event, s);
+ qemu_chr_fe_set_handlers(&s->chr, uart_can_receive, uart_receive,
+ uart_event, s, NULL);
}
}