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authorSoren Brinkmann <soren.brinkmann@xilinx.com>2012-10-12 11:54:37 +0100
committerPeter Maydell <peter.maydell@linaro.org>2012-10-12 11:54:37 +0100
commit884285bf646d93e9dfa4a605bca9f8dc5280b23d (patch)
treecea704e57f3307c3018043e625a0efea5143c6ce /hw/cadence_ttc.c
parentb4ae3cfa57b8c1bdbbd7b7d420971e9171203ade (diff)
cadence_ttc: Fix 'clear on read' behavior
A missing call to qemu_set_irq() when reading the IRQ register required SW to write to the IRQ register to acknowledge an interrupt. With this patch the behavior is fixed: - Reading the interrupt register clears it and updates the timers interrupt status - Writes to the interrupt register are ignored Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/cadence_ttc.c')
-rw-r--r--hw/cadence_ttc.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/hw/cadence_ttc.c b/hw/cadence_ttc.c
index dd02f86eb9..77b6976eda 100644
--- a/hw/cadence_ttc.c
+++ b/hw/cadence_ttc.c
@@ -274,6 +274,7 @@ static uint32_t cadence_ttc_read_imp(void *opaque, target_phys_addr_t offset)
/* cleared after read */
value = s->reg_intr;
s->reg_intr = 0;
+ cadence_timer_update(s);
return value;
case 0x60: /* interrupt enable */
@@ -355,7 +356,6 @@ static void cadence_ttc_write(void *opaque, target_phys_addr_t offset,
case 0x54: /* interrupt register */
case 0x58:
case 0x5c:
- s->reg_intr &= (~value & 0xfff);
break;
case 0x60: /* interrupt enable */