diff options
| author | Klaus Jensen <k.jensen@samsung.com> | 2021-01-18 07:30:50 +0100 |
|---|---|---|
| committer | Klaus Jensen <k.jensen@samsung.com> | 2021-02-08 21:15:53 +0100 |
| commit | ffacaf090893c5d6a5a6ea51b93087411af859c4 (patch) | |
| tree | 4114f5014502199654bfcef67c77a80dd67e8938 /hw/block | |
| parent | c62720f137dffcefa7f03ac1a51b4aadba2a38be (diff) | |
hw/block/nvme: add size to mmio read/write trace events
Add the size of the mmio read/write to the trace event.
Reviewed-by: Minwoo Im <minwoo.im.dev@gmail.com>
Reviewed-by: Keith Busch <kbusch@kernel.org>
Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
Diffstat (limited to 'hw/block')
| -rw-r--r-- | hw/block/nvme.c | 4 | ||||
| -rw-r--r-- | hw/block/trace-events | 4 |
2 files changed, 4 insertions, 4 deletions
diff --git a/hw/block/nvme.c b/hw/block/nvme.c index 09eb1f06e8..2407b6578a 100644 --- a/hw/block/nvme.c +++ b/hw/block/nvme.c @@ -3878,7 +3878,7 @@ static uint64_t nvme_mmio_read(void *opaque, hwaddr addr, unsigned size) uint8_t *ptr = (uint8_t *)&n->bar; uint64_t val = 0; - trace_pci_nvme_mmio_read(addr); + trace_pci_nvme_mmio_read(addr, size); if (unlikely(addr & (sizeof(uint32_t) - 1))) { NVME_GUEST_ERR(pci_nvme_ub_mmiord_misaligned32, @@ -4042,7 +4042,7 @@ static void nvme_mmio_write(void *opaque, hwaddr addr, uint64_t data, { NvmeCtrl *n = (NvmeCtrl *)opaque; - trace_pci_nvme_mmio_write(addr, data); + trace_pci_nvme_mmio_write(addr, data, size); if (addr < sizeof(n->bar)) { nvme_write_bar(n, addr, data, size); diff --git a/hw/block/trace-events b/hw/block/trace-events index 6d1686e6dc..3772502033 100644 --- a/hw/block/trace-events +++ b/hw/block/trace-events @@ -80,8 +80,8 @@ pci_nvme_enqueue_event_noqueue(int queued) "queued %d" pci_nvme_enqueue_event_masked(uint8_t typ) "type 0x%"PRIx8"" pci_nvme_no_outstanding_aers(void) "ignoring event; no outstanding AERs" pci_nvme_enqueue_req_completion(uint16_t cid, uint16_t cqid, uint16_t status) "cid %"PRIu16" cqid %"PRIu16" status 0x%"PRIx16"" -pci_nvme_mmio_read(uint64_t addr) "addr 0x%"PRIx64"" -pci_nvme_mmio_write(uint64_t addr, uint64_t data) "addr 0x%"PRIx64" data 0x%"PRIx64"" +pci_nvme_mmio_read(uint64_t addr, unsigned size) "addr 0x%"PRIx64" size %d" +pci_nvme_mmio_write(uint64_t addr, uint64_t data, unsigned size) "addr 0x%"PRIx64" data 0x%"PRIx64" size %d" pci_nvme_mmio_doorbell_cq(uint16_t cqid, uint16_t new_head) "cqid %"PRIu16" new_head %"PRIu16"" pci_nvme_mmio_doorbell_sq(uint16_t sqid, uint16_t new_tail) "sqid %"PRIu16" new_tail %"PRIu16"" pci_nvme_mmio_intm_set(uint64_t data, uint64_t new_mask) "wrote MMIO, interrupt mask set, data=0x%"PRIx64", new_mask=0x%"PRIx64"" |