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authorVolker RĂ¼melin <vr_qemu@t-online.de>2021-12-26 16:40:17 +0100
committerGerd Hoffmann <kraxel@redhat.com>2022-01-13 10:47:52 +0100
commitecd5f2882fdd10f798984eb52abd00ffc78c2ef7 (patch)
tree704dc10c4539f9649bd9815a9288023eb239e155 /hw/audio
parent9d90ceb27461d7d0d172fd941b812d511794a6c6 (diff)
hw/audio/intel-hda: fix stream reset
Quote from: High Definition Audio Specification 1.0a, section 3.3.35 Offset 80: {IOB}SDnCTL Stream Reset (SRST): Writing a 1 causes the corresponding stream to be reset. The Stream Descriptor registers (except the SRST bit itself) ... are reset. Change the code to reset the Stream Descriptor Control and Status registers except the SRST bit. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/757 Signed-off-by: Volker RĂ¼melin <vr_qemu@t-online.de> Message-Id: <20211226154017.6067-3-vr_qemu@t-online.de> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Diffstat (limited to 'hw/audio')
-rw-r--r--hw/audio/intel-hda.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/hw/audio/intel-hda.c b/hw/audio/intel-hda.c
index 2b55d52150..5f8a878f20 100644
--- a/hw/audio/intel-hda.c
+++ b/hw/audio/intel-hda.c
@@ -581,7 +581,7 @@ static void intel_hda_set_st_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint3
if (st->ctl & 0x01) {
/* reset */
dprint(d, 1, "st #%d: reset\n", reg->stream);
- st->ctl = SD_STS_FIFO_READY << 24;
+ st->ctl = SD_STS_FIFO_READY << 24 | SD_CTL_STREAM_RESET;
}
if ((st->ctl & 0x02) != (old & 0x02)) {
uint32_t stnr = (st->ctl >> 20) & 0x0f;