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authorbalrog <balrog@c046a42c-6fe2-441c-8c8c-71466251a162>2008-05-06 14:45:30 +0000
committerbalrog <balrog@c046a42c-6fe2-441c-8c8c-71466251a162>2008-05-06 14:45:30 +0000
commit57d69a91c41e71ae5f5181c6dedd62dc866234b5 (patch)
tree3117aded9b2aeec63ff5de00702a297054d91068 /hw/arm_gic.c
parentc7b76a0ae374e5ce38d85a859786c7c8c91028ee (diff)
Force correct evaluation order in a a == b != c condition.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4358 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'hw/arm_gic.c')
-rw-r--r--hw/arm_gic.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/hw/arm_gic.c b/hw/arm_gic.c
index 82577301b0..7f67c5276d 100644
--- a/hw/arm_gic.c
+++ b/hw/arm_gic.c
@@ -62,7 +62,7 @@ typedef struct gic_irq_state
#define GIC_TEST_MODEL(irq) s->irq_state[irq].model
#define GIC_SET_LEVEL(irq, cm) s->irq_state[irq].level = (cm)
#define GIC_CLEAR_LEVEL(irq, cm) s->irq_state[irq].level &= ~(cm)
-#define GIC_TEST_LEVEL(irq, cm) (s->irq_state[irq].level & (cm)) != 0
+#define GIC_TEST_LEVEL(irq, cm) ((s->irq_state[irq].level & (cm)) != 0)
#define GIC_SET_TRIGGER(irq) s->irq_state[irq].trigger = 1
#define GIC_CLEAR_TRIGGER(irq) s->irq_state[irq].trigger = 0
#define GIC_TEST_TRIGGER(irq) s->irq_state[irq].trigger