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authorPeter Maydell <peter.maydell@linaro.org>2018-08-16 14:35:50 +0100
committerPeter Maydell <peter.maydell@linaro.org>2018-08-16 14:35:50 +0100
commitbb16c0412a572c2c9cd44496deb3ad430bc49c1a (patch)
treecb87c31c5440a9128cf7762407237b5b57fbed33 /hw/arm
parentc542a9f9794ec8e0bc3fcf5956d3cc8bce667789 (diff)
parentfcf13ca556f462b52956059bf8fa622bc8575edb (diff)
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20180816' into staging
target-arm queue: * Fixes for various bugs in SVE instructions * Add model of Freescale i.MX6 UltraLite 14x14 EVK Board * hw/arm: make bitbanded IO optional on ARMv7-M * Add model of Cortex-M0 CPU * Add support for loading Intel HEX files to the generic loader * imx_spi: Unset XCH when TX FIFO becomes empty * aspeed_sdmc: fix various bugs * Fix bugs in Arm FP16 instruction support * Fix aa64 FCADD and FCMLA decode * softfloat: Fix missing inexact for floating-point add * hw/arm/mps2-tz: Replace init_sysbus_child() with sysbus_init_child_obj() # gpg: Signature made Thu 16 Aug 2018 14:33:41 BST # gpg: using RSA key 3C2525ED14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" # gpg: aka "Peter Maydell <pmaydell@gmail.com>" # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20180816: (30 commits) hw/arm/mps2-tz: Replace init_sysbus_child() with sysbus_init_child_obj() softfloat: Fix missing inexact for floating-point add target/arm: Fix aa64 FCADD and FCMLA decode target/arm: Use FZ not FZ16 for SVE FCVT single-half and double-half target/arm: Use fp_status_fp16 for do_fmpa_zpzzz_h target/arm: Ignore float_flag_input_denormal from fp_status_f16 target/arm: Adjust FPCR_MASK for FZ16 aspeed: add a max_ram_size property to the memory controller aspeed_sdmc: Handle ECC training aspeed_sdmc: Init status always idle aspeed_sdmc: Set 'cache initial sequence' always true aspeed_sdmc: Fix saved values aspeed_sdmc: Extend number of valid registers imx_spi: Unset XCH when TX FIFO becomes empty Add QTest testcase for the Intel Hexadecimal loader: Implement .hex file loader loader: add rom transaction API loader: extract rom_free() function target/arm: add "cortex-m0" CPU model hw/arm: make bitbanded IO optional on ARMv7-M ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/arm')
-rw-r--r--hw/arm/Makefile.objs1
-rw-r--r--hw/arm/armv7m.c39
-rw-r--r--hw/arm/aspeed.c31
-rw-r--r--hw/arm/aspeed_soc.c2
-rw-r--r--hw/arm/fsl-imx6ul.c617
-rw-r--r--hw/arm/mcimx6ul-evk.c85
-rw-r--r--hw/arm/mps2-tz.c32
-rw-r--r--hw/arm/mps2.c1
-rw-r--r--hw/arm/msf2-soc.c1
-rw-r--r--hw/arm/stellaris.c1
-rw-r--r--hw/arm/stm32f205_soc.c1
11 files changed, 772 insertions, 39 deletions
diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
index d51fcecaf2..2902f47b4c 100644
--- a/hw/arm/Makefile.objs
+++ b/hw/arm/Makefile.objs
@@ -36,3 +36,4 @@ obj-$(CONFIG_MSF2) += msf2-soc.o msf2-som.o
obj-$(CONFIG_IOTKIT) += iotkit.o
obj-$(CONFIG_FSL_IMX7) += fsl-imx7.o mcimx7d-sabre.o
obj-$(CONFIG_ARM_SMMUV3) += smmu-common.o smmuv3.o
+obj-$(CONFIG_FSL_IMX6UL) += fsl-imx6ul.o mcimx6ul-evk.o
diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
index 6b07666057..878613994d 100644
--- a/hw/arm/armv7m.c
+++ b/hw/arm/armv7m.c
@@ -211,25 +211,27 @@ static void armv7m_realize(DeviceState *dev, Error **errp)
memory_region_add_subregion(&s->container, 0xe000e000,
sysbus_mmio_get_region(sbd, 0));
- for (i = 0; i < ARRAY_SIZE(s->bitband); i++) {
- Object *obj = OBJECT(&s->bitband[i]);
- SysBusDevice *sbd = SYS_BUS_DEVICE(&s->bitband[i]);
-
- object_property_set_int(obj, bitband_input_addr[i], "base", &err);
- if (err != NULL) {
- error_propagate(errp, err);
- return;
+ if (s->enable_bitband) {
+ for (i = 0; i < ARRAY_SIZE(s->bitband); i++) {
+ Object *obj = OBJECT(&s->bitband[i]);
+ SysBusDevice *sbd = SYS_BUS_DEVICE(&s->bitband[i]);
+
+ object_property_set_int(obj, bitband_input_addr[i], "base", &err);
+ if (err != NULL) {
+ error_propagate(errp, err);
+ return;
+ }
+ object_property_set_link(obj, OBJECT(s->board_memory),
+ "source-memory", &error_abort);
+ object_property_set_bool(obj, true, "realized", &err);
+ if (err != NULL) {
+ error_propagate(errp, err);
+ return;
+ }
+
+ memory_region_add_subregion(&s->container, bitband_output_addr[i],
+ sysbus_mmio_get_region(sbd, 0));
}
- object_property_set_link(obj, OBJECT(s->board_memory),
- "source-memory", &error_abort);
- object_property_set_bool(obj, true, "realized", &err);
- if (err != NULL) {
- error_propagate(errp, err);
- return;
- }
-
- memory_region_add_subregion(&s->container, bitband_output_addr[i],
- sysbus_mmio_get_region(sbd, 0));
}
}
@@ -239,6 +241,7 @@ static Property armv7m_properties[] = {
MemoryRegion *),
DEFINE_PROP_LINK("idau", ARMv7MState, idau, TYPE_IDAU_INTERFACE, Object *),
DEFINE_PROP_UINT32("init-svtor", ARMv7MState, init_svtor, 0),
+ DEFINE_PROP_BOOL("enable-bitband", ARMv7MState, enable_bitband, false),
DEFINE_PROP_END_OF_LIST(),
};
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index bb9d33848d..bb9590f1ae 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -31,6 +31,7 @@ static struct arm_boot_info aspeed_board_binfo = {
typedef struct AspeedBoardState {
AspeedSoCState soc;
MemoryRegion ram;
+ MemoryRegion max_ram;
} AspeedBoardState;
typedef struct AspeedBoardConfig {
@@ -127,6 +128,27 @@ static const AspeedBoardConfig aspeed_boards[] = {
},
};
+/*
+ * The max ram region is for firmwares that scan the address space
+ * with load/store to guess how much RAM the SoC has.
+ */
+static uint64_t max_ram_read(void *opaque, hwaddr offset, unsigned size)
+{
+ return 0;
+}
+
+static void max_ram_write(void *opaque, hwaddr offset, uint64_t value,
+ unsigned size)
+{
+ /* Discard writes */
+}
+
+static const MemoryRegionOps max_ram_ops = {
+ .read = max_ram_read,
+ .write = max_ram_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+};
+
#define FIRMWARE_ADDR 0x0
static void write_boot_rom(DriveInfo *dinfo, hwaddr addr, size_t rom_size,
@@ -187,6 +209,7 @@ static void aspeed_board_init(MachineState *machine,
AspeedBoardState *bmc;
AspeedSoCClass *sc;
DriveInfo *drive0 = drive_get(IF_MTD, 0, 0);
+ ram_addr_t max_ram_size;
bmc = g_new0(AspeedBoardState, 1);
object_initialize(&bmc->soc, (sizeof(bmc->soc)), cfg->soc_name);
@@ -226,6 +249,14 @@ static void aspeed_board_init(MachineState *machine,
object_property_add_const_link(OBJECT(&bmc->soc), "ram", OBJECT(&bmc->ram),
&error_abort);
+ max_ram_size = object_property_get_uint(OBJECT(&bmc->soc), "max-ram-size",
+ &error_abort);
+ memory_region_init_io(&bmc->max_ram, NULL, &max_ram_ops, NULL,
+ "max_ram", max_ram_size - ram_size);
+ memory_region_add_subregion(get_system_memory(),
+ sc->info->sdram_base + ram_size,
+ &bmc->max_ram);
+
aspeed_board_init_flashes(&bmc->soc.fmc, cfg->fmc_model, &error_abort);
aspeed_board_init_flashes(&bmc->soc.spi[0], cfg->spi_model, &error_abort);
diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
index e68911af0f..a27233d487 100644
--- a/hw/arm/aspeed_soc.c
+++ b/hw/arm/aspeed_soc.c
@@ -155,6 +155,8 @@ static void aspeed_soc_init(Object *obj)
sc->info->silicon_rev);
object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc),
"ram-size", &error_abort);
+ object_property_add_alias(obj, "max-ram-size", OBJECT(&s->sdmc),
+ "max-ram-size", &error_abort);
for (i = 0; i < sc->info->wdts_num; i++) {
object_initialize(&s->wdt[i], sizeof(s->wdt[i]), TYPE_ASPEED_WDT);
diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c
new file mode 100644
index 0000000000..258f470623
--- /dev/null
+++ b/hw/arm/fsl-imx6ul.c
@@ -0,0 +1,617 @@
+/*
+ * Copyright (c) 2018 Jean-Christophe Dubois <jcd@tribudubois.net>
+ *
+ * i.MX6UL SOC emulation.
+ *
+ * Based on hw/arm/fsl-imx7.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "qemu-common.h"
+#include "hw/arm/fsl-imx6ul.h"
+#include "hw/misc/unimp.h"
+#include "sysemu/sysemu.h"
+#include "qemu/error-report.h"
+
+#define NAME_SIZE 20
+
+static void fsl_imx6ul_init(Object *obj)
+{
+ FslIMX6ULState *s = FSL_IMX6UL(obj);
+ char name[NAME_SIZE];
+ int i;
+
+ for (i = 0; i < MIN(smp_cpus, FSL_IMX6UL_NUM_CPUS); i++) {
+ snprintf(name, NAME_SIZE, "cpu%d", i);
+ object_initialize_child(obj, name, &s->cpu[i], sizeof(s->cpu[i]),
+ "cortex-a7-" TYPE_ARM_CPU, &error_abort, NULL);
+ }
+
+ /*
+ * A7MPCORE
+ */
+ sysbus_init_child_obj(obj, "a7mpcore", &s->a7mpcore, sizeof(s->a7mpcore),
+ TYPE_A15MPCORE_PRIV);
+
+ /*
+ * CCM
+ */
+ sysbus_init_child_obj(obj, "ccm", &s->ccm, sizeof(s->ccm), TYPE_IMX6UL_CCM);
+
+ /*
+ * SRC
+ */
+ sysbus_init_child_obj(obj, "src", &s->src, sizeof(s->src), TYPE_IMX6_SRC);
+
+ /*
+ * GPCv2
+ */
+ sysbus_init_child_obj(obj, "gpcv2", &s->gpcv2, sizeof(s->gpcv2),
+ TYPE_IMX_GPCV2);
+
+ /*
+ * SNVS
+ */
+ sysbus_init_child_obj(obj, "snvs", &s->snvs, sizeof(s->snvs),
+ TYPE_IMX7_SNVS);
+
+ /*
+ * GPR
+ */
+ sysbus_init_child_obj(obj, "gpr", &s->gpr, sizeof(s->gpr),
+ TYPE_IMX7_GPR);
+
+ /*
+ * GPIOs 1 to 5
+ */
+ for (i = 0; i < FSL_IMX6UL_NUM_GPIOS; i++) {
+ snprintf(name, NAME_SIZE, "gpio%d", i);
+ sysbus_init_child_obj(obj, name, &s->gpio[i], sizeof(s->gpio[i]),
+ TYPE_IMX_GPIO);
+ }
+
+ /*
+ * GPT 1, 2
+ */
+ for (i = 0; i < FSL_IMX6UL_NUM_GPTS; i++) {
+ snprintf(name, NAME_SIZE, "gpt%d", i);
+ sysbus_init_child_obj(obj, name, &s->gpt[i], sizeof(s->gpt[i]),
+ TYPE_IMX7_GPT);
+ }
+
+ /*
+ * EPIT 1, 2
+ */
+ for (i = 0; i < FSL_IMX6UL_NUM_EPITS; i++) {
+ snprintf(name, NAME_SIZE, "epit%d", i + 1);
+ sysbus_init_child_obj(obj, name, &s->epit[i], sizeof(s->epit[i]),
+ TYPE_IMX_EPIT);
+ }
+
+ /*
+ * eCSPI
+ */
+ for (i = 0; i < FSL_IMX6UL_NUM_ECSPIS; i++) {
+ snprintf(name, NAME_SIZE, "spi%d", i + 1);
+ sysbus_init_child_obj(obj, name, &s->spi[i], sizeof(s->spi[i]),
+ TYPE_IMX_SPI);
+ }
+
+ /*
+ * I2C
+ */
+ for (i = 0; i < FSL_IMX6UL_NUM_I2CS; i++) {
+ snprintf(name, NAME_SIZE, "i2c%d", i + 1);
+ sysbus_init_child_obj(obj, name, &s->i2c[i], sizeof(s->i2c[i]),
+ TYPE_IMX_I2C);
+ }
+
+ /*
+ * UART
+ */
+ for (i = 0; i < FSL_IMX6UL_NUM_UARTS; i++) {
+ snprintf(name, NAME_SIZE, "uart%d", i);
+ sysbus_init_child_obj(obj, name, &s->uart[i], sizeof(s->uart[i]),
+ TYPE_IMX_SERIAL);
+ }
+
+ /*
+ * Ethernet
+ */
+ for (i = 0; i < FSL_IMX6UL_NUM_ETHS; i++) {
+ snprintf(name, NAME_SIZE, "eth%d", i);
+ sysbus_init_child_obj(obj, name, &s->eth[i], sizeof(s->eth[i]),
+ TYPE_IMX_ENET);
+ }
+
+ /*
+ * SDHCI
+ */
+ for (i = 0; i < FSL_IMX6UL_NUM_USDHCS; i++) {
+ snprintf(name, NAME_SIZE, "usdhc%d", i);
+ sysbus_init_child_obj(obj, name, &s->usdhc[i], sizeof(s->usdhc[i]),
+ TYPE_IMX_USDHC);
+ }
+
+ /*
+ * Watchdog
+ */
+ for (i = 0; i < FSL_IMX6UL_NUM_WDTS; i++) {
+ snprintf(name, NAME_SIZE, "wdt%d", i);
+ sysbus_init_child_obj(obj, name, &s->wdt[i], sizeof(s->wdt[i]),
+ TYPE_IMX2_WDT);
+ }
+}
+
+static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
+{
+ FslIMX6ULState *s = FSL_IMX6UL(dev);
+ int i;
+ qemu_irq irq;
+ char name[NAME_SIZE];
+
+ if (smp_cpus > FSL_IMX6UL_NUM_CPUS) {
+ error_setg(errp, "%s: Only %d CPUs are supported (%d requested)",
+ TYPE_FSL_IMX6UL, FSL_IMX6UL_NUM_CPUS, smp_cpus);
+ return;
+ }
+
+ for (i = 0; i < smp_cpus; i++) {
+ Object *o = OBJECT(&s->cpu[i]);
+
+ object_property_set_int(o, QEMU_PSCI_CONDUIT_SMC,
+ "psci-conduit", &error_abort);
+
+ /* On uniprocessor, the CBAR is set to 0 */
+ if (smp_cpus > 1) {
+ object_property_set_int(o, FSL_IMX6UL_A7MPCORE_ADDR,
+ "reset-cbar", &error_abort);
+ }
+
+ if (i) {
+ /* Secondary CPUs start in PSCI powered-down state */
+ object_property_set_bool(o, true,
+ "start-powered-off", &error_abort);
+ }
+
+ object_property_set_bool(o, true, "realized", &error_abort);
+ }
+
+ /*
+ * A7MPCORE
+ */
+ object_property_set_int(OBJECT(&s->a7mpcore), smp_cpus, "num-cpu",
+ &error_abort);
+ object_property_set_int(OBJECT(&s->a7mpcore),
+ FSL_IMX6UL_MAX_IRQ + GIC_INTERNAL,
+ "num-irq", &error_abort);
+ object_property_set_bool(OBJECT(&s->a7mpcore), true, "realized",
+ &error_abort);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->a7mpcore), 0, FSL_IMX6UL_A7MPCORE_ADDR);
+
+ for (i = 0; i < smp_cpus; i++) {
+ SysBusDevice *sbd = SYS_BUS_DEVICE(&s->a7mpcore);
+ DeviceState *d = DEVICE(qemu_get_cpu(i));
+
+ irq = qdev_get_gpio_in(d, ARM_CPU_IRQ);
+ sysbus_connect_irq(sbd, i, irq);
+ sysbus_connect_irq(sbd, i + smp_cpus, qdev_get_gpio_in(d, ARM_CPU_FIQ));
+ }
+
+ /*
+ * A7MPCORE DAP
+ */
+ create_unimplemented_device("a7mpcore-dap", FSL_IMX6UL_A7MPCORE_DAP_ADDR,
+ 0x100000);
+
+ /*
+ * GPT 1, 2
+ */
+ for (i = 0; i < FSL_IMX6UL_NUM_GPTS; i++) {
+ static const hwaddr FSL_IMX6UL_GPTn_ADDR[FSL_IMX6UL_NUM_GPTS] = {
+ FSL_IMX6UL_GPT1_ADDR,
+ FSL_IMX6UL_GPT2_ADDR,
+ };
+
+ static const int FSL_IMX6UL_GPTn_IRQ[FSL_IMX6UL_NUM_GPTS] = {
+ FSL_IMX6UL_GPT1_IRQ,
+ FSL_IMX6UL_GPT2_IRQ,
+ };
+
+ s->gpt[i].ccm = IMX_CCM(&s->ccm);
+ object_property_set_bool(OBJECT(&s->gpt[i]), true, "realized",
+ &error_abort);
+
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt[i]), 0,
+ FSL_IMX6UL_GPTn_ADDR[i]);
+
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt[i]), 0,
+ qdev_get_gpio_in(DEVICE(&s->a7mpcore),
+ FSL_IMX6UL_GPTn_IRQ[i]));
+ }
+
+ /*
+ * EPIT 1, 2
+ */
+ for (i = 0; i < FSL_IMX6UL_NUM_EPITS; i++) {
+ static const hwaddr FSL_IMX6UL_EPITn_ADDR[FSL_IMX6UL_NUM_EPITS] = {
+ FSL_IMX6UL_EPIT1_ADDR,
+ FSL_IMX6UL_EPIT2_ADDR,
+ };
+
+ static const int FSL_IMX6UL_EPITn_IRQ[FSL_IMX6UL_NUM_EPITS] = {
+ FSL_IMX6UL_EPIT1_IRQ,
+ FSL_IMX6UL_EPIT2_IRQ,
+ };
+
+ s->epit[i].ccm = IMX_CCM(&s->ccm);
+ object_property_set_bool(OBJECT(&s->epit[i]), true, "realized",
+ &error_abort);
+
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->epit[i]), 0,
+ FSL_IMX6UL_EPITn_ADDR[i]);
+
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->epit[i]), 0,
+ qdev_get_gpio_in(DEVICE(&s->a7mpcore),
+ FSL_IMX6UL_EPITn_IRQ[i]));
+ }
+
+ /*
+ * GPIO
+ */
+ for (i = 0; i < FSL_IMX6UL_NUM_GPIOS; i++) {
+ static const hwaddr FSL_IMX6UL_GPIOn_ADDR[FSL_IMX6UL_NUM_GPIOS] = {
+ FSL_IMX6UL_GPIO1_ADDR,
+ FSL_IMX6UL_GPIO2_ADDR,
+ FSL_IMX6UL_GPIO3_ADDR,
+ FSL_IMX6UL_GPIO4_ADDR,
+ FSL_IMX6UL_GPIO5_ADDR,
+ };
+
+ static const int FSL_IMX6UL_GPIOn_LOW_IRQ[FSL_IMX6UL_NUM_GPIOS] = {
+ FSL_IMX6UL_GPIO1_LOW_IRQ,
+ FSL_IMX6UL_GPIO2_LOW_IRQ,
+ FSL_IMX6UL_GPIO3_LOW_IRQ,
+ FSL_IMX6UL_GPIO4_LOW_IRQ,
+ FSL_IMX6UL_GPIO5_LOW_IRQ,
+ };
+
+ static const int FSL_IMX6UL_GPIOn_HIGH_IRQ[FSL_IMX6UL_NUM_GPIOS] = {
+ FSL_IMX6UL_GPIO1_HIGH_IRQ,
+ FSL_IMX6UL_GPIO2_HIGH_IRQ,
+ FSL_IMX6UL_GPIO3_HIGH_IRQ,
+ FSL_IMX6UL_GPIO4_HIGH_IRQ,
+ FSL_IMX6UL_GPIO5_HIGH_IRQ,
+ };
+
+ object_property_set_bool(OBJECT(&s->gpio[i]), true, "realized",
+ &error_abort);
+
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0,
+ FSL_IMX6UL_GPIOn_ADDR[i]);
+
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0,
+ qdev_get_gpio_in(DEVICE(&s->a7mpcore),
+ FSL_IMX6UL_GPIOn_LOW_IRQ[i]));
+
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 1,
+ qdev_get_gpio_in(DEVICE(&s->a7mpcore),
+ FSL_IMX6UL_GPIOn_HIGH_IRQ[i]));
+ }
+
+ /*
+ * IOMUXC and IOMUXC_GPR
+ */
+ for (i = 0; i < 1; i++) {
+ static const hwaddr FSL_IMX6UL_IOMUXCn_ADDR[FSL_IMX6UL_NUM_IOMUXCS] = {
+ FSL_IMX6UL_IOMUXC_ADDR,
+ FSL_IMX6UL_IOMUXC_GPR_ADDR,
+ };
+
+ snprintf(name, NAME_SIZE, "iomuxc%d", i);
+ create_unimplemented_device(name, FSL_IMX6UL_IOMUXCn_ADDR[i], 0x4000);
+ }
+
+ /*
+ * CCM
+ */
+ object_property_set_bool(OBJECT(&s->ccm), true, "realized", &error_abort);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX6UL_CCM_ADDR);
+
+ /*
+ * SRC
+ */
+ object_property_set_bool(OBJECT(&s->src), true, "realized", &error_abort);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->src), 0, FSL_IMX6UL_SRC_ADDR);
+
+ /*
+ * GPCv2
+ */
+ object_property_set_bool(OBJECT(&s->gpcv2), true,
+ "realized", &error_abort);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpcv2), 0, FSL_IMX6UL_GPC_ADDR);
+
+ /* Initialize all ECSPI */
+ for (i = 0; i < FSL_IMX6UL_NUM_ECSPIS; i++) {
+ static const hwaddr FSL_IMX6UL_SPIn_ADDR[FSL_IMX6UL_NUM_ECSPIS] = {
+ FSL_IMX6UL_ECSPI1_ADDR,
+ FSL_IMX6UL_ECSPI2_ADDR,
+ FSL_IMX6UL_ECSPI3_ADDR,
+ FSL_IMX6UL_ECSPI4_ADDR,
+ };
+
+ static const int FSL_IMX6UL_SPIn_IRQ[FSL_IMX6UL_NUM_ECSPIS] = {
+ FSL_IMX6UL_ECSPI1_IRQ,
+ FSL_IMX6UL_ECSPI2_IRQ,
+ FSL_IMX6UL_ECSPI3_IRQ,
+ FSL_IMX6UL_ECSPI4_IRQ,
+ };
+
+ /* Initialize the SPI */
+ object_property_set_bool(OBJECT(&s->spi[i]), true, "realized",
+ &error_abort);
+
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0,
+ FSL_IMX6UL_SPIn_ADDR[i]);
+
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
+ qdev_get_gpio_in(DEVICE(&s->a7mpcore),
+ FSL_IMX6UL_SPIn_IRQ[i]));
+ }
+
+ /*
+ * I2C
+ */
+ for (i = 0; i < FSL_IMX6UL_NUM_I2CS; i++) {
+ static const hwaddr FSL_IMX6UL_I2Cn_ADDR[FSL_IMX6UL_NUM_I2CS] = {
+ FSL_IMX6UL_I2C1_ADDR,
+ FSL_IMX6UL_I2C2_ADDR,
+ FSL_IMX6UL_I2C3_ADDR,
+ FSL_IMX6UL_I2C4_ADDR,
+ };
+
+ static const int FSL_IMX6UL_I2Cn_IRQ[FSL_IMX6UL_NUM_I2CS] = {
+ FSL_IMX6UL_I2C1_IRQ,
+ FSL_IMX6UL_I2C2_IRQ,
+ FSL_IMX6UL_I2C3_IRQ,
+ FSL_IMX6UL_I2C4_IRQ,
+ };
+
+ object_property_set_bool(OBJECT(&s->i2c[i]), true, "realized",
+ &error_abort);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, FSL_IMX6UL_I2Cn_ADDR[i]);
+
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0,
+ qdev_get_gpio_in(DEVICE(&s->a7mpcore),
+ FSL_IMX6UL_I2Cn_IRQ[i]));
+ }
+
+ /*
+ * UART
+ */
+ for (i = 0; i < FSL_IMX6UL_NUM_UARTS; i++) {
+ static const hwaddr FSL_IMX6UL_UARTn_ADDR[FSL_IMX6UL_NUM_UARTS] = {
+ FSL_IMX6UL_UART1_ADDR,
+ FSL_IMX6UL_UART2_ADDR,
+ FSL_IMX6UL_UART3_ADDR,
+ FSL_IMX6UL_UART4_ADDR,
+ FSL_IMX6UL_UART5_ADDR,
+ FSL_IMX6UL_UART6_ADDR,
+ FSL_IMX6UL_UART7_ADDR,
+ FSL_IMX6UL_UART8_ADDR,
+ };
+
+ static const int FSL_IMX6UL_UARTn_IRQ[FSL_IMX6UL_NUM_UARTS] = {
+ FSL_IMX6UL_UART1_IRQ,
+ FSL_IMX6UL_UART2_IRQ,
+ FSL_IMX6UL_UART3_IRQ,
+ FSL_IMX6UL_UART4_IRQ,
+ FSL_IMX6UL_UART5_IRQ,
+ FSL_IMX6UL_UART6_IRQ,
+ FSL_IMX6UL_UART7_IRQ,
+ FSL_IMX6UL_UART8_IRQ,
+ };
+
+ qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i));
+
+ object_property_set_bool(OBJECT(&s->uart[i]), true, "realized",
+ &error_abort);
+
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0,
+ FSL_IMX6UL_UARTn_ADDR[i]);
+
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
+ qdev_get_gpio_in(DEVICE(&s->a7mpcore),
+ FSL_IMX6UL_UARTn_IRQ[i]));
+ }
+
+ /*
+ * Ethernet
+ */
+ for (i = 0; i < FSL_IMX6UL_NUM_ETHS; i++) {
+ static const hwaddr FSL_IMX6UL_ENETn_ADDR[FSL_IMX6UL_NUM_ETHS] = {
+ FSL_IMX6UL_ENET1_ADDR,
+ FSL_IMX6UL_ENET2_ADDR,
+ };
+
+ static const int FSL_IMX6UL_ENETn_IRQ[FSL_IMX6UL_NUM_ETHS] = {
+ FSL_IMX6UL_ENET1_IRQ,
+ FSL_IMX6UL_ENET2_IRQ,
+ };
+
+ static const int FSL_IMX6UL_ENETn_TIMER_IRQ[FSL_IMX6UL_NUM_ETHS] = {
+ FSL_IMX6UL_ENET1_TIMER_IRQ,
+ FSL_IMX6UL_ENET2_TIMER_IRQ,
+ };
+
+ object_property_set_uint(OBJECT(&s->eth[i]),
+ FSL_IMX6UL_ETH_NUM_TX_RINGS,
+ "tx-ring-num", &error_abort);
+ qdev_set_nic_properties(DEVICE(&s->eth[i]), &nd_table[i]);
+ object_property_set_bool(OBJECT(&s->eth[i]), true, "realized",
+ &error_abort);
+
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->eth[i]), 0,
+ FSL_IMX6UL_ENETn_ADDR[i]);
+
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth[i]), 0,
+ qdev_get_gpio_in(DEVICE(&s->a7mpcore),
+ FSL_IMX6UL_ENETn_IRQ[i]));
+
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth[i]), 1,
+ qdev_get_gpio_in(DEVICE(&s->a7mpcore),
+ FSL_IMX6UL_ENETn_TIMER_IRQ[i]));
+ }
+
+ /*
+ * USDHC
+ */
+ for (i = 0; i < FSL_IMX6UL_NUM_USDHCS; i++) {
+ static const hwaddr FSL_IMX6UL_USDHCn_ADDR[FSL_IMX6UL_NUM_USDHCS] = {
+ FSL_IMX6UL_USDHC1_ADDR,
+ FSL_IMX6UL_USDHC2_ADDR,
+ };
+
+ static const int FSL_IMX6UL_USDHCn_IRQ[FSL_IMX6UL_NUM_USDHCS] = {
+ FSL_IMX6UL_USDHC1_IRQ,
+ FSL_IMX6UL_USDHC2_IRQ,
+ };
+
+ object_property_set_bool(OBJECT(&s->usdhc[i]), true, "realized",
+ &error_abort);
+
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->usdhc[i]), 0,
+ FSL_IMX6UL_USDHCn_ADDR[i]);
+
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->usdhc[i]), 0,
+ qdev_get_gpio_in(DEVICE(&s->a7mpcore),
+ FSL_IMX6UL_USDHCn_IRQ[i]));
+ }
+
+ /*
+ * SNVS
+ */
+ object_property_set_bool(OBJECT(&s->snvs), true, "realized", &error_abort);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, FSL_IMX6UL_SNVS_HP_ADDR);
+
+ /*
+ * Watchdog
+ */
+ for (i = 0; i < FSL_IMX6UL_NUM_WDTS; i++) {
+ static const hwaddr FSL_IMX6UL_WDOGn_ADDR[FSL_IMX6UL_NUM_WDTS] = {
+ FSL_IMX6UL_WDOG1_ADDR,
+ FSL_IMX6UL_WDOG2_ADDR,
+ FSL_IMX6UL_WDOG3_ADDR,
+ };
+
+ object_property_set_bool(OBJECT(&s->wdt[i]), true, "realized",
+ &error_abort);
+
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0,
+ FSL_IMX6UL_WDOGn_ADDR[i]);
+ }
+
+ /*
+ * GPR
+ */
+ object_property_set_bool(OBJECT(&s->gpr), true, "realized",
+ &error_abort);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpr), 0, FSL_IMX6UL_IOMUXC_GPR_ADDR);
+
+ /*
+ * SDMA
+ */
+ create_unimplemented_device("sdma", FSL_IMX6UL_SDMA_ADDR, 0x4000);
+
+ /*
+ * APHB_DMA
+ */
+ create_unimplemented_device("aphb_dma", FSL_IMX6UL_APBH_DMA_ADDR,
+ FSL_IMX6UL_APBH_DMA_SIZE);
+
+ /*
+ * ADCs
+ */
+ for (i = 0; i < FSL_IMX6UL_NUM_ADCS; i++) {
+ static const hwaddr FSL_IMX6UL_ADCn_ADDR[FSL_IMX6UL_NUM_ADCS] = {
+ FSL_IMX6UL_ADC1_ADDR,
+ FSL_IMX6UL_ADC2_ADDR,
+ };
+
+ snprintf(name, NAME_SIZE, "adc%d", i);
+ create_unimplemented_device(name, FSL_IMX6UL_ADCn_ADDR[i], 0x4000);
+ }
+
+ /*
+ * LCD
+ */
+ create_unimplemented_device("lcdif", FSL_IMX6UL_LCDIF_ADDR, 0x4000);
+
+ /*
+ * ROM memory
+ */
+ memory_region_init_rom(&s->rom, NULL, "imx6ul.rom",
+ FSL_IMX6UL_ROM_SIZE, &error_abort);
+ memory_region_add_subregion(get_system_memory(), FSL_IMX6UL_ROM_ADDR,
+ &s->rom);
+
+ /*
+ * CAAM memory
+ */
+ memory_region_init_rom(&s->caam, NULL, "imx6ul.caam",
+ FSL_IMX6UL_CAAM_MEM_SIZE, &error_abort);
+ memory_region_add_subregion(get_system_memory(), FSL_IMX6UL_CAAM_MEM_ADDR,
+ &s->caam);
+
+ /*
+ * OCRAM memory
+ */
+ memory_region_init_ram(&s->ocram, NULL, "imx6ul.ocram",
+ FSL_IMX6UL_OCRAM_MEM_SIZE,
+ &error_abort);
+ memory_region_add_subregion(get_system_memory(), FSL_IMX6UL_OCRAM_MEM_ADDR,
+ &s->ocram);
+
+ /*
+ * internal OCRAM (128 KB) is aliased over 512 KB
+ */
+ memory_region_init_alias(&s->ocram_alias, NULL, "imx6ul.ocram_alias",
+ &s->ocram, 0, FSL_IMX6UL_OCRAM_ALIAS_SIZE);
+ memory_region_add_subregion(get_system_memory(),
+ FSL_IMX6UL_OCRAM_ALIAS_ADDR, &s->ocram_alias);
+}
+
+static void fsl_imx6ul_class_init(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+
+ dc->realize = fsl_imx6ul_realize;
+ dc->desc = "i.MX6UL SOC";
+ /* Reason: Uses serial_hds and nd_table in realize() directly */
+ dc->user_creatable = false;
+}
+
+static const TypeInfo fsl_imx6ul_type_info = {
+ .name = TYPE_FSL_IMX6UL,
+ .parent = TYPE_DEVICE,
+ .instance_size = sizeof(FslIMX6ULState),
+ .instance_init = fsl_imx6ul_init,
+ .class_init = fsl_imx6ul_class_init,
+};
+
+static void fsl_imx6ul_register_types(void)
+{
+ type_register_static(&fsl_imx6ul_type_info);
+}
+type_init(fsl_imx6ul_register_types)
diff --git a/hw/arm/mcimx6ul-evk.c b/hw/arm/mcimx6ul-evk.c
new file mode 100644
index 0000000000..fb2b015bf6
--- /dev/null
+++ b/hw/arm/mcimx6ul-evk.c
@@ -0,0 +1,85 @@
+/*
+ * Copyright (c) 2018 Jean-Christophe Dubois <jcd@tribudubois.net>
+ *
+ * MCIMX6UL_EVK Board System emulation.
+ *
+ * This code is licensed under the GPL, version 2 or later.
+ * See the file `COPYING' in the top level directory.
+ *
+ * It (partially) emulates a mcimx6ul_evk board, with a Freescale
+ * i.MX6ul SoC
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "qemu-common.h"
+#include "hw/arm/fsl-imx6ul.h"
+#include "hw/boards.h"
+#include "sysemu/sysemu.h"
+#include "qemu/error-report.h"
+#include "sysemu/qtest.h"
+
+typedef struct {
+ FslIMX6ULState soc;
+ MemoryRegion ram;
+} MCIMX6ULEVK;
+
+static void mcimx6ul_evk_init(MachineState *machine)
+{
+ static struct arm_boot_info boot_info;
+ MCIMX6ULEVK *s = g_new0(MCIMX6ULEVK, 1);
+ int i;
+
+ if (machine->ram_size > FSL_IMX6UL_MMDC_SIZE) {
+ error_report("RAM size " RAM_ADDR_FMT " above max supported (%08x)",
+ machine->ram_size, FSL_IMX6UL_MMDC_SIZE);
+ exit(1);
+ }
+
+ boot_info = (struct arm_boot_info) {
+ .loader_start = FSL_IMX6UL_MMDC_ADDR,
+ .board_id = -1,
+ .ram_size = machine->ram_size,
+ .kernel_filename = machine->kernel_filename,
+ .kernel_cmdline = machine->kernel_cmdline,
+ .initrd_filename = machine->initrd_filename,
+ .nb_cpus = smp_cpus,
+ };
+
+ object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc),
+ TYPE_FSL_IMX6UL, &error_fatal, NULL);
+
+ object_property_set_bool(OBJECT(&s->soc), true, "realized", &error_fatal);
+
+ memory_region_allocate_system_memory(&s->ram, NULL, "mcimx6ul-evk.ram",
+ machine->ram_size);
+ memory_region_add_subregion(get_system_memory(),
+ FSL_IMX6UL_MMDC_ADDR, &s->ram);
+
+ for (i = 0; i < FSL_IMX6UL_NUM_USDHCS; i++) {
+ BusState *bus;
+ DeviceState *carddev;
+ DriveInfo *di;
+ BlockBackend *blk;
+
+ di = drive_get_next(IF_SD);
+ blk = di ? blk_by_legacy_dinfo(di) : NULL;
+ bus = qdev_get_child_bus(DEVICE(&s->soc.usdhc[i]), "sd-bus");
+ carddev = qdev_create(bus, TYPE_SD_CARD);
+ qdev_prop_set_drive(carddev, "drive", blk, &error_fatal);
+ object_property_set_bool(OBJECT(carddev), true,
+ "realized", &error_fatal);
+ }
+
+ if (!qtest_enabled()) {
+ arm_load_kernel(&s->soc.cpu[0], &boot_info);
+ }
+}
+
+static void mcimx6ul_evk_machine_init(MachineClass *mc)
+{
+ mc->desc = "Freescale i.MX6UL Evaluation Kit (Cortex A7)";
+ mc->init = mcimx6ul_evk_init;
+ mc->max_cpus = FSL_IMX6UL_NUM_CPUS;
+}
+DEFINE_MACHINE("mcimx6ul-evk", mcimx6ul_evk_machine_init)
diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
index 22180c56fb..dc0f34abe5 100644
--- a/hw/arm/mps2-tz.c
+++ b/hw/arm/mps2-tz.c
@@ -107,16 +107,6 @@ static void make_ram_alias(MemoryRegion *mr, const char *name,
memory_region_add_subregion(get_system_memory(), base, mr);
}
-static void init_sysbus_child(Object *parent, const char *childname,
- void *child, size_t childsize,
- const char *childtype)
-{
- object_initialize(child, childsize, childtype);
- object_property_add_child(parent, childname, OBJECT(child), &error_abort);
- qdev_set_parent_bus(DEVICE(child), sysbus_get_default());
-
-}
-
/* Most of the devices in the AN505 FPGA image sit behind
* Peripheral Protection Controllers. These data structures
* define the layout of which devices sit behind which PPCs.
@@ -149,9 +139,9 @@ static MemoryRegion *make_unimp_dev(MPS2TZMachineState *mms,
*/
UnimplementedDeviceState *uds = opaque;
- init_sysbus_child(OBJECT(mms), name, uds,
- sizeof(UnimplementedDeviceState),
- TYPE_UNIMPLEMENTED_DEVICE);
+ sysbus_init_child_obj(OBJECT(mms), name, uds,
+ sizeof(UnimplementedDeviceState),
+ TYPE_UNIMPLEMENTED_DEVICE);
qdev_prop_set_string(DEVICE(uds), "name", name);
qdev_prop_set_uint64(DEVICE(uds), "size", size);
object_property_set_bool(OBJECT(uds), true, "realized", &error_fatal);
@@ -170,8 +160,8 @@ static MemoryRegion *make_uart(MPS2TZMachineState *mms, void *opaque,
DeviceState *iotkitdev = DEVICE(&mms->iotkit);
DeviceState *orgate_dev = DEVICE(&mms->uart_irq_orgate);
- init_sysbus_child(OBJECT(mms), name, uart,
- sizeof(mms->uart[0]), TYPE_CMSDK_APB_UART);
+ sysbus_init_child_obj(OBJECT(mms), name, uart, sizeof(mms->uart[0]),
+ TYPE_CMSDK_APB_UART);
qdev_prop_set_chr(DEVICE(uart), "chardev", serial_hd(i));
qdev_prop_set_uint32(DEVICE(uart), "pclk-frq", SYSCLK_FRQ);
object_property_set_bool(OBJECT(uart), true, "realized", &error_fatal);
@@ -248,8 +238,8 @@ static MemoryRegion *make_mpc(MPS2TZMachineState *mms, void *opaque,
memory_region_init_ram(ssram, NULL, name, ramsize[i], &error_fatal);
- init_sysbus_child(OBJECT(mms), mpcname, mpc,
- sizeof(mms->ssram_mpc[0]), TYPE_TZ_MPC);
+ sysbus_init_child_obj(OBJECT(mms), mpcname, mpc, sizeof(mms->ssram_mpc[0]),
+ TYPE_TZ_MPC);
object_property_set_link(OBJECT(mpc), OBJECT(ssram),
"downstream", &error_fatal);
object_property_set_bool(OBJECT(mpc), true, "realized", &error_fatal);
@@ -288,8 +278,8 @@ static void mps2tz_common_init(MachineState *machine)
exit(1);
}
- init_sysbus_child(OBJECT(machine), "iotkit", &mms->iotkit,
- sizeof(mms->iotkit), TYPE_IOTKIT);
+ sysbus_init_child_obj(OBJECT(machine), "iotkit", &mms->iotkit,
+ sizeof(mms->iotkit), TYPE_IOTKIT);
iotkitdev = DEVICE(&mms->iotkit);
object_property_set_link(OBJECT(&mms->iotkit), OBJECT(system_memory),
"memory", &error_abort);
@@ -421,8 +411,8 @@ static void mps2tz_common_init(MachineState *machine)
int port;
char *gpioname;
- init_sysbus_child(OBJECT(machine), ppcinfo->name, ppc,
- sizeof(TZPPC), TYPE_TZ_PPC);
+ sysbus_init_child_obj(OBJECT(machine), ppcinfo->name, ppc,
+ sizeof(TZPPC), TYPE_TZ_PPC);
ppcdev = DEVICE(ppc);
for (port = 0; port < TZ_NUM_PORTS; port++) {
diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c
index c3946da317..0a0ae867d9 100644
--- a/hw/arm/mps2.c
+++ b/hw/arm/mps2.c
@@ -186,6 +186,7 @@ static void mps2_common_init(MachineState *machine)
g_assert_not_reached();
}
qdev_prop_set_string(armv7m, "cpu-type", machine->cpu_type);
+ qdev_prop_set_bit(armv7m, "enable-bitband", true);
object_property_set_link(OBJECT(&mms->armv7m), OBJECT(system_memory),
"memory", &error_abort);
object_property_set_bool(OBJECT(&mms->armv7m), true, "realized",
diff --git a/hw/arm/msf2-soc.c b/hw/arm/msf2-soc.c
index dbefade644..2702e90b45 100644
--- a/hw/arm/msf2-soc.c
+++ b/hw/arm/msf2-soc.c
@@ -117,6 +117,7 @@ static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp)
armv7m = DEVICE(&s->armv7m);
qdev_prop_set_uint32(armv7m, "num-irq", 81);
qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type);
+ qdev_prop_set_bit(armv7m, "enable-bitband", true);
object_property_set_link(OBJECT(&s->armv7m), OBJECT(get_system_memory()),
"memory", &error_abort);
object_property_set_bool(OBJECT(&s->armv7m), true, "realized", &err);
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
index dc521b4a5a..6c69ce79b2 100644
--- a/hw/arm/stellaris.c
+++ b/hw/arm/stellaris.c
@@ -1304,6 +1304,7 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
nvic = qdev_create(NULL, TYPE_ARMV7M);
qdev_prop_set_uint32(nvic, "num-irq", NUM_IRQ_LINES);
qdev_prop_set_string(nvic, "cpu-type", ms->cpu_type);
+ qdev_prop_set_bit(nvic, "enable-bitband", true);
object_property_set_link(OBJECT(nvic), OBJECT(get_system_memory()),
"memory", &error_abort);
/* This will exit with an error if the user passed us a bad cpu_type */
diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c
index c486d06a8b..980e5af13c 100644
--- a/hw/arm/stm32f205_soc.c
+++ b/hw/arm/stm32f205_soc.c
@@ -109,6 +109,7 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
armv7m = DEVICE(&s->armv7m);
qdev_prop_set_uint32(armv7m, "num-irq", 96);
qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type);
+ qdev_prop_set_bit(armv7m, "enable-bitband", true);
object_property_set_link(OBJECT(&s->armv7m), OBJECT(get_system_memory()),
"memory", &error_abort);
object_property_set_bool(OBJECT(&s->armv7m), true, "realized", &err);