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authorPeter Maydell <peter.maydell@linaro.org>2016-03-04 11:30:16 +0000
committerPeter Maydell <peter.maydell@linaro.org>2016-03-04 11:30:16 +0000
commit8c4f0eb94cc65ee32a12feba88d0b32e3665d5ea (patch)
tree81d58dad781a1e87f2e41094dd721178083b0fb3 /hw/arm
parent2d3b7c0164e1b9287304bc70dd6ed071ba3e8dfc (diff)
target-arm: Correct handling of writes to CPSR mode bits from gdb in usermode
In helper.c the expression (env->uncached_cpsr & CPSR_M) != CPSR_USER is always true; the right hand side was supposed to be ARM_CPU_MODE_USR (an error in commit cb01d391). Since the incorrect expression was always true, this just meant that commit cb01d391 had no effect. However simply changing the RHS here would reveal a logic error: if the mode is USR we wish to completely ignore the attempt to set the mode bits, which means that we must clear the CPSR_M bits from mask to avoid the uncached_cpsr bits being updated at the end of the function. Move the condition into the correct place in the code, fix its RHS constant, and add a comment about the fact that we must be doing a gdbstub write if we're in user mode. Fixes: https://bugs.launchpad.net/qemu/+bug/1550503 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com> Message-id: 1456764438-30015-1-git-send-email-peter.maydell@linaro.org
Diffstat (limited to 'hw/arm')
0 files changed, 0 insertions, 0 deletions