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authorPeter Maydell <peter.maydell@linaro.org>2018-10-16 17:42:56 +0100
committerPeter Maydell <peter.maydell@linaro.org>2018-10-16 17:42:56 +0100
commit09558375a634e17cea6cfbfec883ac2376d2dc7f (patch)
treed9b9e07b71bf83192eb175f423fea97d51a7d013 /hw/arm/virt.c
parentdddb37495b844270088e68e3bf30b764d48d863f (diff)
parent2ef297af07196c29446556537861f8e7dfeeae7b (diff)
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20181016-1' into staging
target-arm queue: * hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART * target/arm: Fix aarch64_sve_change_el wrt EL0 * target/arm: Define fields of ISAR registers * target/arm: Align cortex-r5 id_isar0 * target/arm: Fix cortex-a7 id_isar0 * net/cadence_gem: Fix various bugs, add support for new features that will be used by the Xilinx Versal board * target-arm: powerctl: Enable HVC when starting CPUs to EL2 * target/arm: Add the Cortex-A72 * target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO * target/arm: Mask PMOVSR writes based on supported counters * target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write * coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls # gpg: Signature made Tue 16 Oct 2018 17:42:01 BST # gpg: using RSA key 3C2525ED14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" # gpg: aka "Peter Maydell <pmaydell@gmail.com>" # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20181016-1: coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write target/arm: Mask PMOVSR writes based on supported counters target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO target/arm: Add the Cortex-A72 target-arm: powerctl: Enable HVC when starting CPUs to EL2 net: cadence_gem: Implement support for 64bit descriptor addresses net: cadence_gem: Add support for selecting the DMA MemoryRegion net: cadence_gem: Add support for extended descriptors net: cadence_gem: Add macro with max number of descriptor words net: cadence_gem: Use uint32_t for 32bit descriptor words net: cadence_gem: Disable TSU feature bit target/arm: Fix cortex-a7 id_isar0 target/arm: Align cortex-r5 id_isar0 target/arm: Define fields of ISAR registers target/arm: Fix aarch64_sve_change_el wrt EL0 hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/arm/virt.c')
-rw-r--r--hw/arm/virt.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 96dd4ef10c..9f677825f9 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -712,6 +712,10 @@ static void create_uart(const VirtMachineState *vms, qemu_irq *pic, int uart,
/* Mark as not usable by the normal world */
qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled");
qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay");
+
+ qemu_fdt_add_subnode(vms->fdt, "/secure-chosen");
+ qemu_fdt_setprop_string(vms->fdt, "/secure-chosen", "stdout-path",
+ nodename);
}
g_free(nodename);