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authorNikita Ostrenkov <n.ostrenkov@gmail.com>2024-01-08 14:32:58 +0000
committerPeter Maydell <peter.maydell@linaro.org>2024-01-09 14:42:39 +0000
commitf7f5784af19155df658237d1aae04297d371402b (patch)
treefcdbe6fc81bd419969f8f45d3c89014f7772640a /hw/arm/stm32l4x5_soc.c
parent9468484fe904ab4691de6d9c34616667f377ceac (diff)
hw/arm: add cache controller for Freescale i.MX6
Signed-off-by: Nikita Ostrenkov <n.ostrenkov@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20231219105510.4907-1-n.ostrenkov@gmail.com [PMM: fixed stray whitespace] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/arm/stm32l4x5_soc.c')
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