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| author | Peter Maydell <peter.maydell@linaro.org> | 2015-09-14 14:57:50 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2015-09-14 14:57:50 +0100 |
| commit | 7e4804dafd4689312ef1172b549927a973bb5414 (patch) | |
| tree | 8c1a23075f1fb0a3f435d5676bc89027b50237c3 /hw/arm/fsl-imx31.c | |
| parent | 2b750d9d261bda7f75b39dfc1e1e5f22502929d5 (diff) | |
| parent | f0d574d63f4603ec431f16ad535a555bf7548b94 (diff) | |
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20150914' into staging
target-arm queue:
* fix GIC region size in xlnx-zynqmp
* xlnx-zynqmp: Remove unnecessary brackets
* improve A64 generated TCG code
* add GPIO devices to i.MX25 and i.MX31
* more missing pieces for EL2 support
# gpg: Signature made Mon 14 Sep 2015 14:51:12 BST using RSA key ID 14360CDE
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>"
# gpg: aka "Peter Maydell <pmaydell@gmail.com>"
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
* remotes/pmaydell/tags/pull-target-arm-20150914: (24 commits)
target-arm: Add VMPIDR_EL2
target-arm: Break out mpidr_read_val()
target-arm: Add VPIDR_EL2
target-arm: Suppress EPD for S2, EL2 and EL3 translations
target-arm: Suppress TBI for S2 translations
target-arm: Add VTTBR_EL2
target-arm: Add VTCR_EL2
hw/cpu/{a15mpcore, a9mpcore}: Handle missing has_el3 CPU props gracefully
i.MX: Add GPIO devices to i.MX25 SOC
i.MX: Add GPIO devices to i.MX31 SOC
i.MX: Add GPIO device
target-arm: Use tcg_gen_extrh_i64_i32
target-arm: Recognize ROR
target-arm: Eliminate unnecessary zero-extend in disas_bitfield
target-arm: Recognize UXTB, UXTH, LSR, LSL
target-arm: Recognize SXTB, SXTH, SXTW, ASR
target-arm: Implement fcsel with movcond
target-arm: Implement ccmp branchless
target-arm: Use setcond and movcond for csel
target-arm: Handle always condition codes within arm_test_cc
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/arm/fsl-imx31.c')
| -rw-r--r-- | hw/arm/fsl-imx31.c | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/hw/arm/fsl-imx31.c b/hw/arm/fsl-imx31.c index 87548c8352..8e1ed4811b 100644 --- a/hw/arm/fsl-imx31.c +++ b/hw/arm/fsl-imx31.c @@ -55,6 +55,11 @@ static void fsl_imx31_init(Object *obj) object_initialize(&s->i2c[i], sizeof(s->i2c[i]), TYPE_IMX_I2C); qdev_set_parent_bus(DEVICE(&s->i2c[i]), sysbus_get_default()); } + + for (i = 0; i < FSL_IMX31_NUM_GPIOS; i++) { + object_initialize(&s->gpio[i], sizeof(s->gpio[i]), TYPE_IMX_GPIO); + qdev_set_parent_bus(DEVICE(&s->gpio[i]), sysbus_get_default()); + } } static void fsl_imx31_realize(DeviceState *dev, Error **errp) @@ -184,6 +189,31 @@ static void fsl_imx31_realize(DeviceState *dev, Error **errp) i2c_table[i].irq)); } + /* Initialize all GPIOs */ + for (i = 0; i < FSL_IMX31_NUM_GPIOS; i++) { + static const struct { + hwaddr addr; + unsigned int irq; + } gpio_table[FSL_IMX31_NUM_GPIOS] = { + { FSL_IMX31_GPIO1_ADDR, FSL_IMX31_GPIO1_IRQ }, + { FSL_IMX31_GPIO2_ADDR, FSL_IMX31_GPIO2_IRQ }, + { FSL_IMX31_GPIO3_ADDR, FSL_IMX31_GPIO3_IRQ } + }; + + object_property_set_bool(OBJECT(&s->gpio[i]), false, "has-edge-sel", + &error_abort); + object_property_set_bool(OBJECT(&s->gpio[i]), true, "realized", &err); + if (err) { + error_propagate(errp, err); + return; + } + sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, gpio_table[i].addr); + /* Connect GPIO IRQ to PIC */ + sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0, + qdev_get_gpio_in(DEVICE(&s->avic), + gpio_table[i].irq)); + } + /* On a real system, the first 16k is a `secure boot rom' */ memory_region_init_rom_device(&s->secure_rom, NULL, NULL, NULL, "imx31.secure_rom", |