diff options
| author | Peter Maydell <peter.maydell@linaro.org> | 2022-11-03 13:10:40 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2022-11-04 10:58:58 +0000 |
| commit | d7ef5e16a17c7dd068420c79fa9e893f15b4abaf (patch) | |
| tree | 6abc97f53c9e0339680028fc3cb6f4fdc072bb92 /hw/arm/boot.c | |
| parent | 2b39abb2d6ed022c62eba2d124432d91c52a9d22 (diff) | |
hw/arm/boot: Set SCR_EL3.HXEn when booting kernel
When we direct boot a kernel on a CPU which emulates EL3, we need to
set up the EL3 system registers as the Linux kernel documentation
specifies:
https://www.kernel.org/doc/Documentation/arm64/booting.rst
For CPUs with FEAT_HCX support this includes:
- SCR_EL3.HXEn (bit 38) must be initialised to 0b1.
but we forgot to do this when implementing FEAT_HCX, which would mean
that a guest trying to access the HCRX_EL2 register would crash.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221027140207.413084-3-peter.maydell@linaro.org
Diffstat (limited to 'hw/arm/boot.c')
| -rw-r--r-- | hw/arm/boot.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/hw/arm/boot.c b/hw/arm/boot.c index 17d38260fa..15c2bf1867 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -771,6 +771,9 @@ static void do_cpu_reset(void *opaque) env->cp15.scr_el3 |= SCR_ENTP2; env->vfp.smcr_el[3] = 0xf; } + if (cpu_isar_feature(aa64_hcx, cpu)) { + env->cp15.scr_el3 |= SCR_HXEN; + } /* AArch64 kernels never boot in secure mode */ assert(!info->secure_boot); /* This hook is only supported for AArch32 currently: |