diff options
| author | Cédric Le Goater <clg@kaod.org> | 2019-11-19 15:11:58 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2019-12-16 10:46:34 +0000 |
| commit | 545d6bef7097129040bddc86fe09326ee0a14aae (patch) | |
| tree | c67e2474fd6a48e7373fe719d8147910b21d425a /hw/arm/aspeed_soc.c | |
| parent | 95b56e173e20267778965a2bfd1afd517f7342c4 (diff) | |
aspeed/i2c: Add support for DMA transfers
The I2C controller of the Aspeed AST2500 and AST2600 SoCs supports DMA
transfers to and from DRAM.
A pair of registers defines the buffer address and the length of the
DMA transfer. The address should be aligned on 4 bytes and the maximum
length should not exceed 4K. The receive or transmit DMA transfer can
then be initiated with specific bits in the Command/Status register of
the controller.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Tested-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-id: 20191119141211.25716-5-clg@kaod.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/arm/aspeed_soc.c')
| -rw-r--r-- | hw/arm/aspeed_soc.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c index dd1ee0e333..b01c977441 100644 --- a/hw/arm/aspeed_soc.c +++ b/hw/arm/aspeed_soc.c @@ -311,6 +311,11 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp) } /* I2C */ + object_property_set_link(OBJECT(&s->i2c), OBJECT(s->dram_mr), "dram", &err); + if (err) { + error_propagate(errp, err); + return; + } object_property_set_bool(OBJECT(&s->i2c), true, "realized", &err); if (err) { error_propagate(errp, err); |