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| author | Jamin Lin <jamin_lin@aspeedtech.com> | 2024-10-29 17:17:27 +0800 |
|---|---|---|
| committer | Cédric Le Goater <clg@redhat.com> | 2024-11-04 11:33:13 +0100 |
| commit | 53b316926969d55646b5d6dd8f49e74e440a44f1 (patch) | |
| tree | 52ed41e81d31e4982abda40e81031c3915894291 /hw/arm/aspeed.c | |
| parent | d3d6def468ff18b387ced3de79c0339aa7c1c78d (diff) | |
hw/sd/aspeed_sdhci: Introduce Capabilities Register 2 for SD slot 0 and 1
The size of SDHCI capabilities register is 64bits, so introduces new
Capabilities Register 2 for SD slot 0 (0x144) and SD slot1 (0x244).
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
[ clg: Fixed code alignment ]
Signed-off-by: Cédric Le Goater <clg@redhat.com>
Diffstat (limited to 'hw/arm/aspeed.c')
0 files changed, 0 insertions, 0 deletions