diff options
| author | Peter Maydell <peter.maydell@linaro.org> | 2018-08-20 11:24:33 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2018-08-20 11:24:33 +0100 |
| commit | 514b4f361b65c49303877829561faad5e1d2463c (patch) | |
| tree | 242f8e56e2a7db4d5087033e6d4ff1cd88414775 /hw/arm/armv7m.c | |
| parent | 050c2ea07b18b77c7562512a2b73e86e48c5c4b7 (diff) | |
nvic: Expose NMI line
On real v7M hardware, the NMI line is an externally visible signal
that an SoC or board can toggle to assert an NMI. Expose it in
our QEMU NVIC and armv7m container objects so that a board model
can wire it up if it needs to.
In particular, the MPS2 watchdog is wired to NMI.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Diffstat (limited to 'hw/arm/armv7m.c')
| -rw-r--r-- | hw/arm/armv7m.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c index 878613994d..4bf9131b81 100644 --- a/hw/arm/armv7m.c +++ b/hw/arm/armv7m.c @@ -202,6 +202,7 @@ static void armv7m_realize(DeviceState *dev, Error **errp) */ qdev_pass_gpios(DEVICE(&s->nvic), dev, NULL); qdev_pass_gpios(DEVICE(&s->nvic), dev, "SYSRESETREQ"); + qdev_pass_gpios(DEVICE(&s->nvic), dev, "NMI"); /* Wire the NVIC up to the CPU */ sbd = SYS_BUS_DEVICE(&s->nvic); |